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| hyb18h256321af?12/14/16 hyb18h256321afl14/16/20 256-mbit x32 gddr3 dram rohs compliant data sheet, rev. 1.03, dec. 2005 memory products
edition 2005-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. under no circumstances may the infineon technologies produ ct as referred to in this data sheet be used in 1. any applications that are inte nded for military usage (including but not limited to weaponry), or 2. any applications, devices or systems which are safety cr itical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "critical systems"), if a) a failure of the infineon technologies product can re asonable be expected to - directly or indirectly - (i) have a detrimental effect on such critical systems in terms of reli ability, effectivenes s or safety; or (ii) cause the failure of such critical systems; or b) a failure or malfunction of such cr itical systems can reaso nably be expected to - directly or indirectly - (i) endanger the health or the life of the user of such critical systems or any other person; or (ii) otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). data sheet 3 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 hyb18h256321af?12/14/16 , hyb18h256321afl14/16/20 revision history: rev. 1.03 2005-12 page subjects (major changes since last revision) 87,88 table 35 and table 36 : change all i dd values ( 91-95 table 38 and table 39 : change t rc = t ras + t rp previous revision 1.02 10,12,18,34 and 81 editorial changes: see change list 15 figure 2 : added sen pin 88 table 35 and table 36 : added idd values, (idd5b and idd7 are different from hyb18h512xxx. we listen to your comments any information within this do cument that you feel is wro ng, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com hyb18h256321af[l] 256-mbit gddr3 data sheet 4 rev. 1.03, 2005-12 06302005-ses0-fm0m 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 mirror function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.2 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5 state diagram and truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.1 state diagram for one activated bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5.2 function truth table for more than one activated bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 function truth table for cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 disabling the scan feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 scan initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.1 scan initialization for stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.2 scan initialization in regular sgram operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.3 scan exit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.1 gddr3 io driver and termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.2 self calibration for driver and termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2.3 dynamic switching of dq terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2.4 output impedance and termination dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 extended mode register set command (emrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.1 dll enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.2 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.3 termination rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.4 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.5 low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3.6 vendor code and revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4 mode register set command (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.3 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.4 write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.6 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 bank / row activation (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 writes (wr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.1 write - basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.2 write - basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6.3 write - consecutive bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.3.1 gapless bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.6.3.2 bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.6.4 write with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.6.5 write followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.6.6 write followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table of contents hyb18h256321af[l] 256-mbit gddr3 data sheet 5 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.6.7 write with autoprecharge followed by read / read with autoprecharge . . . . . . . . . . . . . . . . . . . . 52 4.6.8 write followed by precharge on same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.7 reads (rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.7.1 read - basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.7.2 read - basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.7.3 consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.7.3.1 gapless bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.7.4 bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.7.5 read followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.7.6 read with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7.7 read followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.7.8 read followed by precharge on the same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.8 data termination disable (dterdis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.8.1 dterdis followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.2 dterdis followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.8.3 dterdis followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.9 precharge (pre/preall) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 auto refresh command (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.11 self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.11.1 self-refresh entry (srefen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.12 self-refresh exit (srefex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.13 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.14 dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.14.1 frequency range in dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.14.2 initialization in dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.14.3 writes (wr) in dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.14.4 reads (rd) in dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.14.5 self refresh in dll off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1 absolute maximum ratings and operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.2.1 recommended power & dc operation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.4 differential clock dc and ac levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.6 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.7 driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.7.1 driver iv characteristics at 40 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.7.2 termination iv characteristic at 60 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.8 termination iv characteristic at 120 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.9 termination iv characteristic at 240 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.10 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.10.1 operating current ratings (hyb18h256321af?12/14/16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.10.2 operating current ratings (hyb18h256321afl14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.11 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.12 ac timings (hyb18h256321af?12/14/16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.13 ac timings (hyb18h256321afl14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.1 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.2 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 data sheet 6 rev. 1.03, 2005-12 hyb18h256321af[l] 256-mbit gddr3 figure 1 ballout 256-mbit graphics ram [top view, mf = low] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3 state diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4 internal block diagram (reference only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5 scan capture timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6 scan shift timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7 scan initialization for stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8 scan initialization sequence within regular sgram mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9 boundary scan exit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10 power up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11 output driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12 termination update keep out time after autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13 self calibration of pmos and nmos legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14 odt disable timing during a read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16 extended mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17 extended mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18 timing of vendor code and revision id generation on dq[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 20 mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23 bank activating timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 24 clock, cke and command/address timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 26 basic write burst / dm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 27 write basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 28 gapless write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 29 consecutive write bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 30 write with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 31 write followed by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 32 write command followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 33 write with autoprecharge followed by read or read with autoprecharge on another bank. . . . . . 52 figure 34 write followed by precharge on same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 36 basic read burst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 37 read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 38 gapless consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 39 consecutive read bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 40 read command followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 41 read with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 42 read followed by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 43 read followed by precharge on the same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 45 dterdis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 46 dterdis command followed by dterdis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 47 dterdis command followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 48 dterdis command followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 50 precharge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 52 auto refresh cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 53 self-refresh entry command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 54 self refresh entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 56 self refresh exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 58 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 59 dll off: power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 60 dll off: write followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 61 write followed by precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 62 dll off: read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 63 dll off: read followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of figures data sheet 7 rev. 1.03, 2005-12 hyb18h256321af[l] 256-mbit gddr3 figure 64 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 65 40 ohm driver pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 66 60 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 67 120 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 68 240 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 69 pg-tfbga 136 package (11mm x 14mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 data sheet 8 rev. 1.03, 2005-12 hyb18h256321af[l] 256-mbit gddr3 table 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 ball assignment with mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4 command overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6 minimum delay from rd/a and wr/a to any other command (to another bank) with concurrent autoprecharge 19 table 7 function truth table i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 function truth table ii (cke table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9 boundary scan exit) order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10 scan pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11 scan dc electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12 scan ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13 scan ac electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14 range of external resistance zq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15 termination types and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16 number of legs used for terminator and driver self calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18 revision id and vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20 mapping of wdqs and dm signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21 ba1 and ba0 precharge bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 22 dll off: general timing parameter for hyb18h256321afl14/16/20 . . . . . . . . . . . . . . . . . . . . . . 73 table 23 general timing parameter for hyb18h256321afl14/16/20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 24 read timing parameter for hyb18h256321afl14/16/20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 25 self refresh exit timing parameter for hyb18h256321afl14/16/20. . . . . . . . . . . . . . . . . . . . . . 78 table 26 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 27 power & dc operation conditions.(0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 28 dc & ac logic input levels (0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 29 differential clock dc an d ac input conditions (0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . 81 table 30 pin capacitances (vddq = 1.8v, ta = 25c, f= 1mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 31 programmed driver iv characteristics at 40 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 32 programmed terminator characteristics at 60 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 33 programmed terminator characteristics of 120 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 34 programmed terminator characteristic at 240 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 35 operating current ratings (0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 36 operating current ratings (0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 37 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 38 timing parameters (hyb18h256321af?12/14/16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 39 timing parameters (hyb18h256321afl14/16/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 40 pg-tfbga 136 package thermal resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 list of tables data sheet 9 rev. 1.03, 2005-12 06302005-ses0-fm0m 256-mbit x32 gddr3 dram hyb18h256321af[l] hyb18h256321af?12/14/16 hyb18h256321afl14/16/20 1overview 1.1 features ? 2.0 v v ddq io voltage (hyb18h256321af?12/14/16) ? 2.0 v v dd core voltage (hyb18h256321af?12/14/16) ? 1.8 v v ddq io voltage (hyb18h256321afl14/16/20) ? 1.8 v v dd core voltage (hyb18h256321afl14/16/20) ? organization: 2048k 32 4 banks ? 4096 rows and 512 columns (128 burst start locations) per bank ? differential clock in puts (clk and clk ) ? cas latencies of 7 8, 9, 10, 11 ? write latencies of 3, 4 ? burst sequence with length of 4, 8. ? 4n pre fetch ? short ras to cas timing for writes ? t ras lockout support ? t wr programmable for writes with auto-precharge ? data mask for write commands ? single ended read strobe (rdqs) per byte. rdqs edge-aligned with read data ? single ended write strobe (wdqs) per by te. wdqs center-aligned with write data ? dll aligns rdqs and dq transitions with clock ? programmable io interface including on chip termination (odt) ? autoprecharge option with concurrent auto precharge support ? 4k refresh (32ms) ? autorefresh and self refresh ? pg-tfbga 136 package (11mm 14mm) ? calibrated output drive. active termination support ? rohs compliant product 1) 1)rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercur y, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominat ed biphenyl ethers. hyb18h256321af[l] 256-mbit gddr3 overview data sheet 10 rev. 1.03, 2005-12 06302005-ses0-fm0m 1.2 description the infineon 256-mbit x32 gddr3 dram is a high speed memory device, designed for high bandwidth intensive applications like pc graphics systems. the chip?s 4 bank architecture is optimized for high speed. hyb18h256321af[l] uses a double data rate interface and a 4 n -pre fetch architecture. the gddr3 interface transfers two 32 bit wide data words per clock cycl e to/from the i/o pins. corresponding to the 4 n -pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-cycle data transfers at the i/o pins. single-ended unidirectional read and write data strobes are transmitted simultaneously with read and write data respectively in order to capture data properly at the re ceivers of both the graphics sdram and the controller. data strobes are organized per byte of the 32 bit wide interface. for read commands the rdqs are edge-aligned with data, and the wdqs are center-aligned with data for write commands. the hyb18h256321af[l] operates from a differential clock (clk and clk ). commands (addresses and control signals) are registered at ever y positive edge of clk. input data is regi stered on both edges of wdqs, and output data is referenced to both edges of rdqs. in this document references to ?the positive edge of cl k? imply the crossing of the positive edge of clk and the negative edge of clk . similarly, the ?negative edge of clk? refers to the crossing of the negative edge of clk and the positive edge of clk . references to rdqs are to be interp reted as any or all rdqs<3:0>. wdqs, dm and dq should be interpre ted in a similar fashion. read and write accesses to the hyb18h256321af[l] are burst oriented. the burst length is fixed to 4 and 8 and the two least significant bits of the bu rst address are ?don?t care? and internally set to low. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command ar e used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the column location for the burst access. each of the 4 banks consists of 4096 row locations and 512 column locations. an auto precharge function can be combined with read and write to provide a self-timed row precharge that is initiated at the end of the burst access. the pi pe lined, multibank architectu re of the hyb18h256321af[l] allows for concurrent operation, thereby providing high ef fective bandwidth by hiding row precharge and activation time. the ?on die termination? interface (odt) is optimized for high frequency digital data transfers and is internally controlled. the termination resistor value can be set using an external zq resistor or disabled through the extended mode register. the output driver impedance can be set using the extended mode register. it can either be set to zq / 6 (auto calibration) or to 35, 40 or 45 ohms. auto refresh and power down with self refresh operations are supported. a standard jedec pg-tfbga 136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former ddr graphics sdram products. table 1 ordering information part number 1) 1) hyb: designator for memory components 18h: v ddq = 1.8 v 256: 256-mbit density 32: organization a: product revision f: lead- and halogen-free l: low power product organisation clock (mhz) package hyb18h256321af?12/14/16 32 800/700/600 pg-tfbga 136 hyb18h256321afl14/16/20 700/600/500 data sheet 11 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration 2 pin configuration figure 1 ballout 256-mbit graphics ram [top view, mf = low] cke v dd v ss ba0 ck a9 a11 dm2 dq24 dq25 v ssq dm0 dq4 dq6 dq5 dq17 v ref v ssq v ddq v ssq v ss a1 rfu a10 a7 a2 a5 v ss rdqs0 dq3 dq7 v ss 123 ba1 dq12 dq9 mf v dd 7 dm1 dq0 v ssq v ddq v ss v dd 8 v ddq v ddq dq8 dq11 dq15 dq13 9 4 5 6 10 11 12 zq dq1 v ddq dq2 v ddq v ssq wdqs0 v ssq v ddq v ddq v dd v ss v ssq rfu v ddq v dd a0 a4 v dd dq27 a3 v ddq dq26 dm3 v ddq v ssq wdqs3 rdqs3 v ssq v ddq dq28 dq29 v ddq v ssq dq30 dq31 v ssq v ddq v dd v ss sen v ssq v ddq dq10 v ddq v ssq rdqs1 wdqs1 v ssq v ddq v ddq cas ras cs dq14 v dd we v ssq rfm v ref v ddq ck v ss a6 a8/ap v dd v ssq v ss dq19 dq16 dq18 v ddq v ssq rdqs2 wdqs2 v ssq dq21 dq20 v ddq v ssq dq23 dq22 v ssq reset v ss v dd v ddq a b c d f g h j e l m k n p t v r hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 12 rev. 1.03, 2005-12 06302005-ses0-fm0m 2.1 ball definition and description table 2 ball description ball type detailed function clk, clk input clock: clk and clk are differential clock inputs. address and command inputs are latched on the positive edge of clk. gr aphics sdram outputs (rdqs, dqs) are referenced to clk. clk and clk are not interna lly terminated. cke input clock enable: cke high activates and cke low de activates the internal clock and input buffers. taking cke low provides power down. if all banks are precharged, this mode is called precharge power do wn and self refresh mode is entered if a auto refresh command is issued. if at least one bank is open, active power down mode is entered and no self refresh is allowed. all input receivers except clk, clk and cke are disabled during power down. in self refresh mode the clock receivers are disabled too. self refresh exit is performed by setting cke asynchronously high. exit of power down without self refresh is accomplished by se tting cke high with a positive edge of clk. the value of cke is latched asynchronously by reset during power on to determine the value of the termination resistor of the address and command inputs. cke is not allowed to go low during a rd, a wr or a snoop burst. cs input chip select: cs enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands with the exception of dterdis are ignored, but internal operations continue. cs is one of the four command balls. ras , cas , we input command inputs: sampled at the positive edge of clk, cas , ras , and we define (together with cs ) the command to be executed. dq<0:31> i/o data input/output: the dq signals form the 32 bit data bus. during reads the balls are outputs and during writes they are inputs. data is transferred at both edges of rdqs. dm<0:3> input input data mask: the dm signals are input mask sign als for write data. data is masked when dm is sampled high with the write data . dm is sampled on both edges of wdqs. dm0 is for dq<0:7>, dm1 is for dq<8:15> , dm2 is for dq<16:23> and dm3 is for dq<24:31>. although dm balls are input-only, their loading is designed to match the dq and wdqs balls. rdqs<0:3> output read data strobes: rdqsx are unidirectional strobe signals. during reads the rdqsx are transmitted by the graphics sdram and edge-aligned with data. rdqs have preamble and postamble requirements. rdqs0 is for dq<0:7>, rdqs1 for dq<8:15>, rdqs2 for dq<16:23> and rdqs3 for dq<24:31>. wdqs<0:3> input write data strobes: wdqsx are unidirectional strobe signals. during writes the wdqsx are generated by the controller and center aligned with data. wdqs have preamble and postamble requirements. wdqs0 is for dq<0:7>, wdqs1 for dq<8:15>, wdqs2 for dq<16:23> and wdqs3 for dq<24:31>. ba<0:1> input bank address inputs: ba select to which internal ban k an activate, read, write or precharge command is being applied. ba ar e also used to distinguish between the mode register set and extende d mode register set commands. a<0:11> input address inputs: during activate, a0-a11 defines the row address. for read/write, a2-a7 and a9 defines the column address, and a8 defines the auto precharge bit. if a8 is high, the accessed bank is precharged after ex ecution of the column access. if a8 is low, auto precharge is disabled and t he bank remains active. sampled with precharge, a8 determines whether one bank is precharged (selected by ba<0:1>, a8 low) or all 4 banks are precharged (a8 high). during (extended) mode register set the address inputs define the register se ttings. a<0:11> are sampled with the positive edge of clk. data sheet 13 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration 2.2 mirror function the gddr3 graphics ram provides a ball mirroring featur e that is enabled by applying a logic high on ball mf. this function allows for efficient rout ing in a clam shell configuration. depending of the logic stat e applied on mf, the command and address signals will be assigned to different balls. the default ball configuration (see figure 1 ) corresponds to mf = low. the dc level (high or low) must be applied on the mf pi n at power up and is not allowed to change after that. table 3 shows the ball assignment as a function of the logic state applied on mf. zq - odt impedance reference: the zq ball is used to control the odt impedance. reset input reset pin: the res pin is a v ddq cmos input. res is not internally terminated. when res is at low state the chip go es into full reset. the chip st ays in full reset until res goes to high state. the low to high transition of the res signal is used to latch the cke value to set the value of the termination resistor s of the address and command inputs. after exiting the full reset a complete initialization is required since the full reset sets the internal settings to default. mf input mirror function pin: the mf pin is a v ddq cmos input. this pin must be hardwired on board either to a power or to a ground plane. with mf set to high, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. sen input enables boundary scan functionality. if boundary sc an is not used pin should be constantly connected to gnd. v ref supply voltage reference: v ref is the reference voltage input. v dd , v ss supply power supply: power and ground for the internal logic. v ddq , v ssq supply i/o power supply: isolated power and ground for the output buffers to provide improved noise immunity. rfm - when the mf ball is tied lo w, rfm receiver is disabled and it recommended to be driven to a static low state. however, either static high or floati ng state on this pin will not cause any problem for the gddr3 sgram. when th e mf ball is tied high, ras(h3) becomes rfm due to mirror function and the receiver is disabled. it is recommended to be driven to a static low state. however, ei ther static high or floating st ate on this pin will not cause any problem for the gddr3 sgram. table 3 ball assignment with mirror mf logic state signal low high h3 h10 ras f4 f9 cas h9 h4 we f9 f4 cs h4 h9 cke k4 k9 a0 h2 h11 a1 k3 k10 a2 m4 m9 a3 table 2 ball description ball type detailed function hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 14 rev. 1.03, 2005-12 06302005-ses0-fm0m k9 k4 a4 h11 h2 a5 k10 k3 a6 l9 l4 a7 k11 k2 a8 m9 m4 a9 k2 k11 a10 l4 l9 a11 g4 g9 ba0 g9 g4 ba1 table 3 ball assignment with mirror (cont?d) mf logic state signal low high data sheet 15 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration 2.3 functional block diagram figure 2 functional block diagram & r o x p q ' h f r g h u 6 h q v h $ p s o l i l h u v d q g ' d w d % x v % x i i h u 0 h p r u \ $ u u d \ % d q n [ [ e l w & r o x p q ' h f r g h u 6 h q v h $ p s o l i l h u v d q g ' d w d % x v % x i i h u & r o x p q ' h f r g h u 6 h q v h $ p s o l i l h u v d q g ' d w d % x v % x i i h u & r o x p q ' h f r g h u 6 h q v h $ p s o l i l h u v d q g ' d w d % x v % x i i h u 0 h p r u \ $ u u d \ [ [ e l w 0 h p r u \ $ u u d \ [ [ e l w 0 h p r u \ $ u u d \ [ [ e l w % d q n % d q n % d q n 5 r z ' h f r g h u 5 r z ' h f r g h u 5 r z ' h f r g h u 5 r z ' h f r g h u , q s x w % x i i h u v 2 x w s x w % x i i h u v & / . & / . & . ( ' / / ' 4 ' 4 ' d w d ' 0 5 ' 4 6 : ' 4 6 ' 4 ' 4 ' d w d ' 0 5 ' 4 6 : ' 4 6 ' 4 ' 4 ' d w d ' 0 5 ' 4 6 : ' 4 6 ' 4 ' 4 ' d w d ' 0 5 ' 4 6 : ' 4 6 5 r z $ g g u h v v % x i i h u & r o x p q $ g g u h v v % x i i h u & r o x p q $ g g u h v v h v $ $ $ 5 h i u h v k & r x q w h u & r q w u r o / r j l f 7 l p l q j * h q h u d w r u $ g g u h v v e x i i h u $ $ $ $ $ 3 $ $ % $ % $ 0 r g h 5 h j l v w h u $ $ 3 & 6 5 $ 6 & $ 6 : ( = 4 5 ( 6 5 r z $ g g u h v v h v $ $ % $ % $ 6 ( 1 hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 16 rev. 1.03, 2005-12 06302005-ses0-fm0m 2.4 commands 2.4.1 command table in the following table cken refers to the positive edge of clk corresponding to the clock cycle when the command is given to the graphics sdram. cken-1 refers to th e previous positive edge of clk. for all command and address inputs cken is implied. all input states or sequences no t shown are illegal or reserved. abbreviations: ba: bank address; col.: column address table 4 command overview operation code cke n-1 cke n cs ras cas we ba0 ba1 a8 a2-7 a9-11 note device deselect desel h h h l x h x x h x l h xxx 1) 1) x represents ?don?t care?. data terminator disable dterdis h h h h l h x x x x 1)2) 2) this command is invoked when a read is issued on another dr am rank placed on the same command bus. cannot be in power- down or self refresh state. the r ead command will cause the data term ination to be disabled. refer to figure 14 for timing. no operation nop h h l h h h x x x x mode register set mrs h h l l l l 0 0 opcode extended mode register set emrs h h l l l l 1 0 opcode bank activate act h h l l h h ba ba row address 1)3) 3) ba0 - ba1 provide bank address, a0 - a11 provide the row address. read rd h h l h l h ba ba l col. 1)4) 4) ba0 - ba1 provide bank address, a2- a7, a9 provide the column address, a8/ap controls auto precharge. read w/ autoprecharg e rd/a h h l h l h ba ba h col. 1)4) write wr h h l h l l ba ba l col. 1)4) write w/ autoprecharg e wr/a h h l h l l ba ba h col. 1)4) precharge pre h h l l h l ba ba l x 1) precharge all preall h h l l h l x x h x 1) auto refresh aref h h l l l h x x x x 1)5) 5) auto refresh and self refresh entry differ only by the state of cke. power down mode entry pwdnen h l h l x h x h x h xxxx 1)6) 6) pwdnen is selected by issuing a desel or nop at the firs t positive clk edge following the hi gh to low transition of cke. power down mode exit pwdnex l h x x x x x x x x 1)7) 7) first possible valid command after t xpn . during t xpn only nop or desel commands are allowed. self refresh entry srefen h l l l l h x x x x 1)8) 8) self refresh is selected by issuing aref at the first po sitive clk edge following the high to low transition of cke. self refresh exit srefex l h x x x x x x x x 1)9) 9) first possible valid command after t xsc . during t xsc only nop or desel commands are allowed. data sheet 17 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration 2.4.2 description of commands table 5 description of commands command description desel the desel function prevents new commands fr om being executed by th e graphics sdram. the graphics sdram is effectively deselected. operations in progress are not affected. nop the nop command is used to perform a no oper ation to the graphics sdram, which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mrs the mode register is loaded via address inputs a0 - a11. for more details see ?mode register set command (mrs)? on page 40 . the mrs command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. emrs the extended mode register is loaded via addr ess inputs a0 - a11. for more details see section ?extended mode register set command (emrs)? on page 37 . the emrs command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. act the act command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 - ba1 inputs selects the bank, and the address provided in inputs a0 - a11 selects the row. this row remains active (or open) for accesses until a precharge (pre, rd/a, or wr/a command) is issued to that bank. a precharge must be issued before opening a different row in the same bank. rd the rd command is used to initiate a burst read access to an active row. the value on the ba0 - ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the row will remain open for subsequent accesses. for rd commands the value on a8 is set low. rd/a the rd/a command is used to initiate a burst read access to an active row. the value on the ba0 - ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the value on input a8 is set high. the row being access ed will be prechar ged at the end of the read burst. the same individual-bank precharge function is performed like it is described for the pre command. auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. the user must not issue a new act command to the same bank until the precharge time (t rp ) is completed. this time is determined as if an explicit pre command was issued at the earliest possible time as described in section ?reads (rd)? on page 54 . wr the wr command is used to init iate a burst write access to an active row. the value on the ba0 - ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the row will remain open for subsequent accesses. for wr commands the value on a8 is set low. input data appearing on the dqs is written to the memory array depending on the value on the dm input appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed for that byte / column location. hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 18 rev. 1.03, 2005-12 06302005-ses0-fm0m wr/a the wr/a command is used to initiate a burst wr ite access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the value on input a8 is set high. the row being access ed will be prechar ged at the end of the write burst. the same individual-bank precharge function is performed which is described for the pre command. auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. the user is not allowed to issue a new act to the same bank until the precharge time (t rp ) is completed. this time is determined as if an explicit pre command was issued at the earliest possible time as described in section ?writes (wr)? on page 44 . input data appearing on the dqs is written to the memory array depending on the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. pre the pre command is used to deactivate the open row in a pa rticular bank. the bank will be available for a subsequent row access a specified time ( t rp ) after the pre command is issued. inputs ba0 - ba1 select the bank to be precharge d. a8/ap is set to low. once a bank has been precharged, it is in the idle state and must be activated again prior to any rd or wr commands being issued to that bank. a pre command will be tr eated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. preall the preall command is used to deactivate a ll open rows in the memory device. the banks will be available for a subsequent row access a specified time ( t rp ) after the preall command is issued. once the banks have been precharged, they are in th e idle state and must be activated prior to any read or write commands being issued. the preall command will be treated as a nop for those banks where there is no open row, or if a previously open row is already in the process of precharging. preall is issued by a pre command with a8/ap set to high. aref the aref is used during normal operation of the gddr3 graphics ram to refresh the memory content. the refresh addressing is generated by t he internal refresh controller. this makes the address bits ?don?t care? during an aref command. the hyb18h256321af[l] requires aref cycles at an average periodic interval of t refi (max). to improve efficiency a maximum number of eight aref commands can be posted to one memory device (with t rfc from aref to aref) as described in section ?auto refresh command (aref)? on page 69 . this means that the maximum absolute interval between any aref command is 8 x t refi (max). this maximum absolute interval is to allow the gddr3 gr aphics ram output drivers and internal terminators to recalibrate, compensating for voltage and temperature changes. all banks must be in the idle state before issuing the aref command. they will be simultaneously refr eshed and return to the idle st ate after aref is completed. t rfc is the minimum required time between an aref command and a following act/aref command. srefen the self refresh function can be used to reta in data in the gddr3 grap hics ram even if the rest of the system is powered down. when entering th e self refresh mode by issuing the srefen command, the gddr3 graphics ram retains dat a without external clocking. the srefen command is initiated like an aref command e xcept cke is disabled (low). the dll is automatically disabled upon entering self refres h mode and automatically enabled and reset upon exiting self refresh. (1000 cycles must then occur before a rd or dterdis command can be issued) the active terminations re main enabled during self refresh. input signals except cke are ?don?t care?. if two gddr3 graphics rams share the same command and address bus, self refresh may be entered only for the two devices at the same time. table 5 description of commands command description data sheet 19 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration srefex the srefex command is used to exit the se lf refresh mode. the dll is automatically enabled and reset upon exiting. the procedure for exiti ng self refresh requires a sequence of commands. first clk and clk must be stable prior to cke going fr om low to high. once cke is high, the gddr3 graphics ram must receive only nop/desel commands until t xsnr is satisfied. this time is required for the completion of any internal refr esh in progress. a simple algorithm for meeting both refresh, dll requirements and output calibration is to apply nops for 1000 cycles before applying any other command to allow the dll to lo ck and the output driv ers to recalibrate. pwdnen the pwdnen command enables the power down mode . it is entered when cke is set low together with a nop/desel. the cke signal is sampled at the risi ng edge of the cloc k. once the power down mode is initiated, all of the receiver circuits except clk and cke are gated off to reduce power consumption. the dll remains active (unless disa bled before with emrs). all banks can be set to idle state or stay active. duri ng power down mode, refresh oper ations cannot be performed; therefore the refresh conditions of the chip have to be considered and if necessary power down state has to be left to perform an auto refres h cycle. if two gddr3 graphics rams share the same command and address bus, power down may be enter ed only for the two devices at the same time. pwdnex a cke high value sampled at a low to high transition of clk is required to exit power down mode. once cke is high, the gddr3 graphics ram must receive only nop/d esel commands until t xpn is satisfied. after t xpn any command can be issued, but it has to comply with the state in which the power down mode was entered. dterdis data termination disable (bus snooping for rd commands): the da ta termination disable command is detected by the device by snooping the bus for rd commands excluding cs . the gddr3 graphics ram will disable its data term inators when a rd comma nd is detected. the terminators are disabled starting at cl - 1 clocks after the rd command is detected and the duration is 4 clocks. in a two rank system, both dram devi ces will snoop the bus for rd commands to either device and both will disable thei r terminators if a rd command is detect ed. the command and address terminators are always enabled. see figure 14 for an example of when the data terminators are disabled during a rd command. table 6 minimum delay from rd/a and wr/a to any other command (to another bank) with concurrent autoprecharge from command to command minimum delay to another bank (with concurrent auto precharge) note wr/a rd or rd/a (wl + 2) t ck + t wtr wr or wr/a 2 t ck pre t ck act t ck rd/a rd or rd/a 2 t ck wr or wr/a (cl + 4 - wl) t ck pre t ck act t ck table 5 description of commands command description hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 20 rev. 1.03, 2005-12 06302005-ses0-fm0m 2.5 state diagram and truth tables 2.5.1 state diagram for one activated bank the following diagram shows all possible states and transi tions for one activated bank. the other 3 banks of the graphics sdram are assumed to be in idle state. figure 3 state diagram for one bank note: mrs, emrs, auto refresh, self refresh and pr echarge power down are only allowed if all 4 banks are idle. idle self refresh power down active precharge auto refresh act pre wr/a rd/a pden pdex pdex pden mrs emrs sren srex active wr rd single bank all banks data sheet 21 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 pin configuration 2.5.2 function truth table for more than one activated bank if there is more than one bank activated in the graphics sdram, some commands can be performed in parallel due to the chip?s multibank archit ecture. the following table defines for which commands such a scheme is possible. all other transitions are illegal. notes 1-11 define the start and end of the actions belonging to a submitted command. this table is based on the assumption that there are no other actions ongoing on bank n or bank m. if there are any actions ongoing on a third bank t rrd , t rtw and t wtr have to be taken always into account. table 7 function truth table i current state ongoing action on bank n possible action in parallel on bank m active activate 1) 1) action activate starts with issu ing the command and ends after t rcd . act, pre, write, write/a, read, read/a 2) 2) during action activate an act command on another bank is allowed considering t rrd , a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. write 3) 3) action write starts with issuing the command and ends twr af ter the first pos. edge of clk following the last falling wdqs edge. act, pre, write, write/a, read, read/a 4) 4) during action write an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank must be separated by at least one nop from the ongoing write. rd or rd/a are not allowed before t wtr is met. write/a 5) 5) action write/a starts with issuing the command and ends twr af ter the first positive edge of clk following the last falling wdqs edge. act, pre, write, write/a, read 6) 6) during action write/a an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank has to be separated by at least one nop from the ongoing command. rd is not allowed before twtr is met. rd/a is not allowed during an ongoing write/a action. read 7) 7) action read starts with issuing the command and ends with th e first positive edge of clk following the last falling edge of rdqs. act, pre, write, write/a, read, read/a 8) 8) during action read and read/a an act or a pre command on another bank is allowed any time. a new rd or rd/a command on another bank has to be separated by at least one nop from the ongoing command. a wr or wr/a command on another bank has to meet t rtw . read/a 9) 9) action read/a starts with issuing the co mmand and ends with the first positive edg e of clk following the last falling edge of rdqs. act, pre, write, write/a, read, read/a precharge 10) 10) action precharge and pre charge all start with issuing the command and ends after t rp . act, pre, write, write/a, read, read/a 11) 11) during action active an act command on another banks is allowed considering t rrd . a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. precharge all - power down entry 12) 12) during power down and self refresh only the exit commands are allowed. - idle activate 1) act power down entry - auto refresh 13) - self refresh entry - mode register set (mrs) 14) - extended mrs - power down power down exit 15) - self refresh self refresh exit 16) - hyb18h256321af[l] 256-mbit gddr3 pin configuration data sheet 22 rev. 1.03, 2005-12 06302005-ses0-fm0m 2.6 function truth table for cke note: 1. cken is the logic step at clock edge n; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr3 grap hics ram immediately prior to clock edge n. 3. command is the command registered at clock edge n, and action is a result of command. 4. all states and sequ ences not shown are illegal or reserved. 5. desel or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of 1000 clock cycles is required before applying any other valid command. 13) auto refresh starts with issu ing the command and ends after t rfc . 14) actions mode register set and extended mode regist er set start with issuing the command and ends after t mrd . 15) action power down exit starts with issuing the command and ends after t xpn . 16) action self refresh exit starts with issuing the command and ends after t xsc . table 8 function truth table ii (cke table) cke n-1 cke n current state command action l l power down x stay in power down self refresh x stay in self refresh l h power down desel or nop exit power down self refresh desel or nop exit self refresh 5 h l all banks idle desel or no p entry precharge power down bank(s) active desel or no p entry active power down all banks idle auto refr esh entry self refresh data sheet 23 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 boundary scan 3 boundary scan 3.1 general description the 256m gddr3 incorporates a modified boundary scan te st mode. this mode doesn?t operate in accordance with ieee standard 1149. 1-1990. to save the current gddr3 ball-out, this mode will scan t he parallel data input and output the scanned data through the wdqs0 pin controlled by sen. 3.2 disabling the scan feature it is possible to operate the 256mb gddr3 without usin g the boundary scan feature. sen (at u-4 of 136- ball package) should be tied low(vss) to prevent the devi ce from entering the boundary scan mode. the other pins which are used for scan mode, res, mf, wdqs0 and cs will be operating at normal gddr3 functionalities when sen is deasserted. figure 4 internal block diagram (reference only) ck d dq ck d dq ck d dq ck d dq dm0 dq5 dq4 rdqs0 res (ssh, scan shift) mf (soe, output enable) wdqs0 (sout, scan out) sen, scan enable puts device into scan mode and re-maps pins to scan functionality the following lists the rest of the signals on the scan chain: dq[3:0], dq[31:6], rdqs[3:1], wdqs[3:1], dm[3:1], cas, we, cke, ba[1:0], a[11:0], ck, ck and zq the following lists the signals not on the scan chain: vdd, vss, vddq, vssq, vdda, vssa and vref two rfu?s (j-2 and j-3 on 136-ball package) and nc (h-10) will be on the scan chain and will read as a logic "0" cs (sck, scan clock) dedicated scan flops (1 per signal under test) pins under test tie to logic 0 hyb18h256321af[l] 256-mbit gddr3 boundary scan data sheet 24 rev. 1.03, 2005-12 06302005-ses0-fm0m notes 1. when the device is in sca n mode, the mirror function will be disabl ed and none of the pins are remapped. 2. since the other input of the mux for dm0 tied to gnd, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. two rfu balls (#56 and #57) in th e scan order, will read as a logic?0?. table 9 boundary scan exit) order bit# ball bit# ball bit# ball bit# ball bit# ball bit# ball 1 d-3 13 e-10 25 k-11 37 r-10 49 l-3 61 g-4 2 c-2 14 f-10 26 k-10 38 t-11 50 m-2 62 f-4 3 c-3 15 e-11 27 k-9 39 t-10 51 m-4 63 f-2 4 b-2 16 g-10 28 m-9 40 t-3 52 k-4 64 g-3 5 b-3 17 f-11 29 m-11 41 t-2 53 k-3 65 e-2 6 a-418g-930l-1042r-354k-266f-3 7 b-10 19 h-9 31 n-11 43 r-2 55 l-4 67 e-3 8 b-1120h-1032m-1044p-356j-3 9 c-10 21 h-11 33 n-10 45 p-2 57 j-2 10 c-11 22 j-11 34 p-11 46 n-3 58 h-2 11 d-10 23 j-10 35 p-10 47 m-3 59 h-3 12 d-11 24 l-9 36 r-11 48 n-2 60 h-4 data sheet 25 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 boundary scan notes 1. when sen is asserted, no commands are to be executed by the gddr3. this applies both to user commands and manufacturing commands which may exist while res is deasserted. 2. the scan function can be used right after bringing up v dd / v ddq of the device. no init ialization sequence of the device is required. after leaving the scan function it is required to run through the complete initialization sequence. 3. in scan mode all te rminations for cmd/add and dq, dm, rdqs and wdqs are switched off. 4. in a double-load clam-shell config uration, sen will be asserted to both devices. separate two soe ?s should be provided to top and bottom devices to access the sc anned output. when either of the devices is in scan mode, soe for the other device which is not in a scan will be disabled. table 10 scan pin description package ball symbol normal function type description v-9 ssh res input scan shift: capture the data input from the pad at logic low and shift the data on the chain at logic high. f-9 sck cs input scan clock: not a true clock, could be a single pulse or series of pulses. all scan inputs will be re ferenced to risi ng edge of the scan clock d-2 sout wdqs0 output scan output v-4 sen sen input scan enable: logic high enables the device into scan mode and will be disabled at logic low. must be tied to gnd when not in use. a-9 soe mf input scan output enable: enables (registered low) and disables (registered high) sout data . this pin will be tied to v dd or gnd through a resistor (typically 1k ? for normal operation. tester needs to overdrive this pin to guarantee the required input logic level in scan mode. table 11 scan dc electrical characte ristics and operating conditions parameter/condition symbol min max units notes input high (logic 1) voltage v ih (dc) v ref +0.15 ? 1)2) 1) the parameter applies only when sen is asserted. 2) all voltages referenced to gnd. input low (logic 0) voltage - v il (dc) ? v ref -0.15 v 1)2) hyb18h256321af[l] 256-mbit gddr3 boundary scan data sheet 26 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 5 scan capture timing figure 6 scan shift timing table 12 scan ac electrical characteristics parameter/condition symbol min max units notes clock clock cycle time t sck 40 ? ns 1 scan command time scan enable setup time t ses 20 ? ns 1)2 scan enable hold time t seh 20 ? ns 1 scan command setup time for ssh, soe and sout t scs 14 ? ns 1 scan command hold time for ssh, soe and sout t sch 14 ? ns 1 scan capture time scan capture setup time t sds 10 ? ns 1 scan capture hold time t sdh 10 ? ns 1 sck sen t sds t sdh pins under test don't care valid t ses ssh son t scs low sck sen t ses ssh son t scs t scs son t sac t soh scan out bit 0 scan out bit 1 scan out bit 2 scan out bit 3 don't care data sheet 27 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 boundary scan notes 1. the parameter applies only when sen is asserted. 2. scan enable should be issued earlier than other scan commands by 6 ns. 3.3 scan initialization the initialization sequence for the boundary scan functi onality depends on the intended sgram operation mode. there are two modes to distinguish. the first mode is the stand-alone mode. in the stand-alone mode the sgram is supposed to support the boundary scan func tionality only, the user does not intend to operate the dram in its ordinary function ality after or prior to the entering of the boundary scan functionality. the purpose of the stand-alone mode could be a connectivi ty test at the manufacturing site. the second mode is the regular sgram functionality. with this common mode the boundary scan functionality can be enabled after the sgram has been initialized by the regular power-up and sgram initialization sequence. when the boundary scan functionality is left the regul ar sgram initialization sequence has to be re-iterated. 3.3.1 scan initialization for stand-alone mode the sgram needs to follow the given sequence to support the boundary scan functionality in the stand-alone mode. there is no external clock for the whole sequence needed. sequence flow: 1.) external voltages (vdd/vddq/vref) need to be stable for 200us, sen has to be kept low 2.) bring sen up to high state to enter boundary scan functionality 3.) operate boundary scan func tionality according to the scan features given in chapter 3.2 4.) boundary scan can be exited by bringing sen low or simply by switching power off the scan initialization sequ ence for the stand-alone mode is shown in figure 7. scan shift time scan clock to valid scan output t sac ??ns1 scan clock to scan output hold t soh 1.5 ? ns 1 table 12 scan ac electrical characteristics parameter/condition symbol min max units notes hyb18h256321af[l] 256-mbit gddr3 boundary scan data sheet 28 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 7 scan initialization for stand-alone mode 3.3.2 scan initialization in regular sgram operation the initialization sequence of the boundary scan functiona lity in regular sgram operat ion has to follow the given sequence. sequence flow: 1.) external voltages (vdd/vddq/vref) need to be stable for 200us, res has to be kept low, external clock has to be stable prior to res goes high 2.) bring res high and keep clock stable for 700tcks, cke will be latched by rising res edge, keep tath/tats 3.) bring sen up to high state to enter boundary scan functionality 4.) operate boundary scan func tionality accordingly to the scan features given in chapter 3.2 5.) boundary scan can be exited by bringing sen low 6.) wait t sn for bringing up res, prior to bringing r es to high state external has to be stable 7.) after res is at high state wait 700tck 8.) continue with regular initializat ion sequence (pre-all, emrs, mrs) the steps 1 and 2 are necessary to enable the termination for the command/address pins. they are part of the regular sgram initialization. they are required if the user wants to issue commands between to entering of the boundary scan functionality and the power-up sequence. the entering of the boundary scan mode is resetting the command/address termination values and all emrs/mrs sett ings. therefore they have to be initialized again after the boundary scan fu nctionary has been left. figure 8 shows the scan initialization sequence for regular sgram operation. t = 200s v dd v ddq v ref ssh [res] sen sck[cs#] soe[mf] t ses t scs sout[wdqs] pins under test boundary scan mode t scs t sch t scs t sch t scs scan out bit 0 power-up: vdd /vddq/vref stabl e don't care clk/clk# t sds t sdh valid t sds t sdh valid data sheet 29 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 boundary scan figure 8 scan initialization sequence within regular sgram mode cke t = 200s v dd v ddq v ref ssh[res] t ats t ath reset at power - up 700tck sen valid sck[#cs] soe[mf] t ses t scs sout[wdqs] t sds t sdh valid pins under test boundary scan mode t scs t sch t scs t sch t scs scan out bit 0 power-up: vdd stable don't care clk/clk# valid t sds t sdh t sds t sdh hyb18h256321af[l] 256-mbit gddr3 boundary scan data sheet 30 rev. 1.03, 2005-12 06302005-ses0-fm0m 3.3.3 scan exit sequence figure 9 shows the scan exit sequence. this figure show the exiting of the boundary scan functionality in conjugation with the appended regular sgram initializati on sequence to bring the sgram again in a well defined state. figure 9 boundary scan exit sequence table 13 scan ac electrical parameters parameter cas latency symbo l limit values unit notes min max t resl t resl 20 - ns t sn t sn 20 - ns cke res t ats t ath sen t resl t sn standard power up sequence starting with pre all 700tck clk/ clk# stable clock sout invalid data sheet 31 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4 functional description 4.1 initialization the hyb18h256321af[l] must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefi ned operation or permanent damage to the device. the following sequence is high ly recommended for power-up: 1. apply power ( v dd , v ddq , v ref ). apply v dd before or at the same time as v ddq , apply v ddq before or at the same time as v ref . maintain res=l and cs=h to ens ure that all the dq outputs will be in hiz state, all active terminations off and the dll off. all other pins may be undefined. 2. maintain stable conditions for 200 s minimum for the hyb18h256321af[l] to power up. 3. after clock is stable, set cke to high or low. after t ats minimum set res to high. on the rising edge of res, the cke value is latched to determine the address and command bus te rmination value. if cke is sampled low the address termination value is set to zq / 2. if cke is sampled high, the address and command bus termination is set to zq. 4. after tath minimum, set cke to high. 5. wait a minimum of 700 cycles to calibrate and update the address and command termination impedances. issue deselect on th e command bus during these 700 cycles. 6. apply a precharge all command, followed by an extended mode register command after t rp is met and activate the dll. 7. issue an mode register set command after t mrd is met to reset the dll and define the operating parameters. 8. wait 1000 cycles of clock input to lock the dll. no read command can be applied during this time. since the impedance calibration is already completed, the dll mimic circui try can use the actual prog rammed driver impedance value. 9. issue a precharge all command or issue 4 single bank precharge commands, one to each of the 4 banks to place the chip in an idle state. 10. issue two or more auto refresh commands. hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 32 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 10 power up sequence clk# clk cke min. 200 s com . v dd v ddq v ref res t ats t ath mrs pa t rp arf t mrd act arf t rfc t rfc t rp cycles 1000 vdd and clk stable don't care pa: preall command a.c.: any command arf: auto refresh command t mrd emr mrs: mrs command with dll reset emr: emrs command des : deselect dm a0-a7, a9-a11 code code pa ra a 8 all banks code code all banks ra ba0 = h, ba1 = l ra ba0 = l, ba1 = l ba0, ba1 rdqs wdqs dq 700 cycles des des data sheet 33 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.2 programmable impedance output drivers and active terminations 4.2.1 gddr3 io driver and termination the is equipped with programmable impedance output buffe rs and active terminations . this allows the user to match the driver impedance to the system impedance. to adjust the impedance of dq<0:31> and rdqs<0:3>, an external precision resistor (zq) is connected between the zq pin and vss. the value of the resistor must be six times the value of the de sired impedance. for example, a 240 ? resistor is required for an output impedance of 40 ? . the range of zq is 210 ? to 270 ? , giving an output impedance range of 35 ? to 45 ? (one sixth the value of zq within 10%). the value of zq is used to calib rate the internal dq termination resistors of dq<0:31>, wdqs<0:3> and dm<0:3>. the two termination values that are sele ctable using emrs[3:2] are zq / 4 and zq / 2. the value of zq is also used to calibrate the inte rnal address command termination resistors. the inputs terminated in this manner are a<0:11>, cke, cs , ras , cas , we . the two termination values that are selectable upon power up (cke latched low to high transition of res) are zq/2 and zq. res, mf, clk and clk are not interna lly terminated. if no resistance is connected to zq , an internal default value of 240 ? will be used. in this case, no calibration will be performed. figure 11 output driver simplified schematic table 14 range of external resistance zq parameter symbol min nom max units notes external resistance value zq 210 240 270 ? table 15 termination types and activation ball termination type termination activation clk, clk , rdqs<0:3>, zq, res, mf no termination cke, cs , ras , cas , we , ba0 - ba1, a<0:11> add / cmds always on dm<0:3>, wdqs<0:3>, dq always on dq<0:31> dq cmd bus snooping vssq vddq dq read to other rank output data read data enable zq/4 or zq/2 terminator when receiving zq/6 driver when transmitting hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 34 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.2.2 self calibration for driver and termination the output impedance is updated during all aref commands. these updates are used to compensate for variations in supply voltage and temperature. impedance updates do not affect device operation. no activity on the address, command and data bus is allowed during a minimum keep out time t ko after the autorefresh command has been issued. figure 12 termination update keep out time after autorefresh command to guarantee optimum driver impedance after power- up, the hyb18h256321af[l] needs 700 cycles after the clock is applied and stable to calibrate the impedance upon power-up. the user can operate the part with fewer than 700 cycles, but optimal output impedance will not be g uaranteed. the gddr3 graphics ram proceeds in the following manner for self calibration: the pmos device is calibrated against the external zq re sistor value. first one pmos leg is calibrated against zq. the number of legs used for the terminators (dq and add/cmd) and the pmos driver is represented in table 16 . next, one nmos leg is calibrated against the already calibrated pmos leg. the nmos driver uses 6 nmos legs. clk# clk don't care t ko com. arf: autorefresh arf add. dq keep out time nop data sheet 35 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description figure 13 represents a simplified schematic of the calibration ci rcuits. first, the strength control bits are adjusted in such a way that the vddq voltage is divided equally between the pmos device and the zq resistor. the best bit pattern will cause the comparator to switch the pmos match signal output value. in a second step, the nfet is calibrated against the already calib rated pfet. in the same manner, the best control bit combination will cause the comparator to switch the nm os match signal output value. figure 13 self calibration of pmos and nmos legs table 16 number of legs used for terminator and driver self calibration termination number of legs notes cke (at res) terminator add / cmd 0 zq/2 2 1zq1 emrs[3:2] dq 00 disabled 0 1) 1) emrs[3:2] = 00 disables the add and cmd terminations as well. 10 zq/4 4 11 zq/2 2 driver pmos zq/6 6 nmos zq/6 6 vddq strength control [2:0] vssq match vddq / 2 zq pmos calibration vssq vddq strength control [2:0] vssq match vddq / 2 nmos calibration hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 36 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.2.3 dynamic switchi ng of dq terminations the gddr3 graphics ram will disable its data terminators when a read or dterdis command is detected. the terminators are disabled starting at cl - 1 clocks af ter the read / dterdis command is detected and the duration is 4 clocks. in a two rank system, both de vices will snoop the bus for a read / dterdis command to either device and both will disable th eir terminators if a read / dterdis command is detect ed. the address and command terminators are always enabled. figure 14 odt disable timing during a read command 4.2.4 output impedance and terminatio n dc electrical characteristics the driver and termination impedances are determined by applying v ddq/2 nominal at the corresponding input / output and by measuring the current flowing into or out of the device. v ddq is set to the nominal value. i oh is the current flowing out of dq when the pull-up transistor is activated and the dq termination disabled. i ol is the current flowing into dq when the pull-down transistor is activa ted and the dq termination disabled. i tcah(zq) is the current flowing out of the termination of commands and addresses for a zq termination value. table 17 dc electrical characteristics parameter nom. unit notes zq value 240 ? min max i oh zq/6 20.5 25.0 ma 1) 1) measurement performed with v ddq (nominal) and by applying v ddq/2 at the corresponding input / output. 0 c tc 85 c i ol zq/6 20.5 25.0 ma 1) i tcah(zq) zq 3.4 4.2 ma 1) clk# clk rd n/d n/d com . n/d n/d n/d n/d n/d 012567 8 b / c addr. cas latency = 7 rdqs dq b / c: bank / column address rd: read d3 d2 d1 d0 9 n/d n/d data terminations are disabled dq termination don't care dx: data from b / c com.: command addr.: address b / c n/d: nop or deselect 10 11 data sheet 37 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.3 extended mode regi ster set command (emrs) figure 15 extended mode register set command the extended mode register is used to set the output driver impedance value, the termination impedance value, the write recovery time value for write with autoprecharge. it is used as well to enable/disable the dll, to issue the vendor id and to enable/disable the low power mode. there is no default value for the extended mode register. therefore it must be written after power up to operate the gddr3 graphics ram. the extended mode register can be programmed by performing a normal mode register set operation and setting the ba0 bit to high. all other bits of the emr register are reserved and should be set to low. the extended mode register must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation ( figure 16 ). the timing of the emrs command operation is equivalent to the timing of the mrs command operation. figure 16 extended mode register bitmap 1. these settings are for debugging purposes only. 2. default termination values at power up. 3. the odt disable function disables all terminators on the device. 4. if the user activates bits in the extended mode register in an optional field, either the optional field is activated (if option implemented in the device ) or no action is taken by the device (if option not implemented). 5. wr (write recovery time for auto precharge) in clock cycles is calculated by dividing t wr (in ns) and rounding up to the next integer (wr[cycles] = t wr [ns] / t ck [ns]). the mode register must be programmed to this value. clk# clk ras# cke cas# we# a0-a11 ba0 1 don't care cod: code to be loaded in t the register cs# cod ba1 0 data z ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01 a11 a10 dll v rfu wr rtt a11 0 1 self- refresh 8ms 32ms a2 0 1 a3 0 0 0 1 1 1 odt disabled rfu termination zq / 4 zq / 2 (default) 2) 1 output drive r impedance autocal 35 0 40 45 1 a0 a1 1 1 0 0 0 1 wr 11 4 05 6 1 a4 a5 1 1 0 0 0 lp a10 0 1 vendor id on off a6 0 1 dll enable enable disable a7 0 0 0 0 07 10 0 1 wr 18 0 1 09 1 1 1 1 1 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 38 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 17 extended mode register set timing 4.3.1 dll enable the dll must be enabled for normal oper ation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll. (when the device exits self-refresh mode, the dll is enabled automatically). anyt ime the dll is enabled, 1000 cycles must occur before a read command can be issued. 4.3.2 wr the wr parameter is programmed using the register bits a4, a5 and a7. this integer parameter defines as a number of clock cycles the write recovery ti me in a write with autoprecharge operation. the following inequality has to be complied with: wr * t ck t wr , where t ck is the clock cycle time. 4.3.3 termination rtt the data termination, rtt, is used to set the value of the intern al termination resistors. the gddr3 dram supports zq / 4 and zq / 2 termination values. the termination may also be disabled for testing and other purposes. 4.3.4 output driver impedance the output driver impedance extended mode register is used to set the value of the data output driver impedance. when the auto calibration is us ed, the output driver impedance is set nominally to zq / 6. if the output driver impendance is changed to 30, 40 or 45 ohms the user needs to issue 16 aref commands separated by t rfc consecutively to make the change effective. the user must be aware that the command bus needs to be stable for a time of t ko after each aref. 4.3.5 low power when the low power extended mode register is set, the de vice changes its internal self-refresh rate from 32 ms to 8 ms. this allows self-refresh operation at higher temperatures for mobile applications. clk# clk don't care pa emrs nop a.c. nop t rp t mrd command emrs: extended mrs command pa: preall command a.c.: any command nop data sheet 39 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.3.6 vendor code and revision identification the manufacturer vendor code is selected by issuing an extended mode register set command with bit a10 set to 1 and bits a0-a9 and a11 set to the desired value. when the vendor code function is enabled the gddr3 dram will provide the infineon vendor code on dq[3:0] and the revision id entification on dq[7:4]. the code will be driven onto the dq bus after tridon following the emrs command that sets a10 to 1. the vendor code and revision id will be driven on dq[7:0 ] until a new emrs command is issued with a10 set back to 0. after trdoff following the second emrs command, the data bus is driven back to high. this second emrs command must be issued before initiating any subsequ ent operation. violating this requirement will result in unspecified operation. note: please refer to revision release note for revision id value figure 18 timing of vendor code and revision id generation on dq[7:0] table 18 revision id and vendor code revision identificati on infineon vendor code dq[7:4] dq[3:0] 0000 0010 clk# clk n/d n/d com. n/d n/d n/d n/d 01234567 8 add a[9:0], a11 9 10 n/d n/d rdqs dq[7:0] a10 n/d add emrs emrs t ridon vendor code and revision id t ridoff emrs: extended mode register set command add: address don't care n/d: nop or deselect hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 40 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.4 mode register set command (mrs) figure 19 mode register set command the mode register stores the data for controlling the operating modes of the memory. it programs cas latency, test mode, dll reset and the value of the write latency. there is no default value for the mode register; therefore it must be written after power up to operate the . during a mode register set command the address inputs are sampled and stored in the mode register. t mrd must be met before any command can be issued to the graphics sdram. th e mode register contents can only be set or changed when the graphics sdram is in idle state. figure 20 mode register bitmap clk# clk ras# cke cas# we# a0-a11 ba0 1 don't care cod: code to be loaded in t the register cs# cod ba1 0 dll tm cas latency dll reset 00 bl cas latency bt ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a11 a10 wl a8 0 1 dll reset yes no write latency burst length bl a2 a1 a0 all others 010 rfu 4 latency a6 a5 a4 all others 10 010 8 000 9 001 1 1 1 7 rfu a7 0 1 mode normal testmode testmode a3 0 1 bt sequential rfu burst type wl a11 a10 a9 all others 4 100 3 011 rfu a0 note: 1) the dll reset command is self-clearing 011 8 11 011 data sheet 41 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description figure 21 mode register set timing 4.4.1 burst length read and write accesses to the gddr3 graphics ram are burst or iented with burst length of 4 and 8. this value must be programmed using the mode register set command (a0 .. a2). the burst length determines the number of column locations that can be accesse d for a given read or write command. when a read or write command is iss ued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block if a boundary is reached. the starting location within this block is determined by the two least signi ficant bits a0 and a1 which are set internally to the fixed value of zero each. reserved states should not be used, as unknown operation or incompatibility with future versions may result. 4.4.2 burst type accesses within a given bank must be programmed to be se quential. this is done using the mode register set command (a3). this device does no t support the burst interleave mode. the value applied at the balls a0 and a1 for the column address is ?don?t care? 4.4.3 cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data as shown on figure 37 . if a read command is registered at cl ock edge n, and the latency is m clo cks, the data will be available nominally coincident with clock edge n+m. reserved states should not be used as unknown operati on or incompatibility with futu re versions may result. table 19 burst definition burst length starting column address order of accesses within a burst (type = sequential) a2 a1 a0 4 ? x x 0-1-2-3 8 0 x x 0-1-2-3-4-5-6-7 1 x x 4-5-6-7-0-1-2-3 clk# clk pa mrs nop a.c. nop t rp t mrd com. nop rd nop don't care mrs: mrs command pa: preall command a.c.: any other command as read t mrdr rd: read command hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 42 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.4.4 write latency the write latency, wl, is the delay, in clock cycles, bet ween the registration of a write command and the availability of the first bit of input data as shown in figure 27 . 4.4.5 test mode the normal operating mode is selected by issuing a mode register set command with bit a7 set to zero and bits a0-a6 and a8-a11 set to the desired value. 4.4.6 dll reset the normal operating mode is selected by issuing a mode register set command with bit a8 set to zero and bits a0-a7 and a9-a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one and bits a0-a 7 and a9-a11 set to the desired va lues. the gddr3 graphics ram returns automatically in the normal mode of operations once the dll reset is completed. data sheet 43 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.5 bank / row activation (act) figure 22 activating a specific row before a read or write command can be issued to a bank, a row in that bank must be opened. this is accomplished via the act command, which selects both the bank and the row to be activated. after opening a row by issuing an act command, a read or write command may be issued after t rcd to that row. a subsequent act command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successi ve act commands to the same bank is defined by t rc . a subsequent act command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive act commands to different banks is defined by t rrd . there is a minimum time t ras between opening and closing a row. figure 23 bank activating timing clk# clk ras# cke cas# we# a0-a11 ba0-ba1 ra ba ra: row addres s ba: bank addres s don't care cs# clk# clk t rrd t rcd t ras t rc act act r/w com. pre act row row col a0-a11 a8 row b.x b.y b.y ba0-ba1 b.y b.y row: row address col: column address don't care b.x: bank x b.y: bank y r/w: read or write comma n pre: precharge command act: activate command hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 44 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 24 clock, cke and command/address timings setup and hold timing for cke is equal to cmd and addr setu p and hold timing. 4.6 writes (wr) 4.6.1 write - basic information figure 25 write command write bursts are initiated with a wr command, as shown in figure 25 . the column and bank addresses are provided with the wr command, and auto precharge is either enabled or disabled for that access. the length of the burst initiated with a wr command is four or eight depending on the mode register setting. there is no interruption of wr bursts. the two least significant address bits a0 and a1 are ?don?t care?. for wr commands with autoprecharge the row being accessed is precharged t wr/a after the completion of the burst. if t ras (min) is violated the begin of the internal autoprecharge will be perf ormed one cycle after t ras (min) is met. wr, the writ e recovery time for write with autoprecharge can be programmed in the mode register. choosing high va lues for wr will prevent the chip to delay the internal autoprecharge in order to meet t ras (min). during wr bursts data will be registered with the edges of wdqs. the write latency can be programmed during extended mode register set. the first valid data is registered with the first valid rising edge of wdqs following the wr command. the externally provided wdqs must switch from high to low at the beginning of the preamble. there is also a postamble requirement before the wdqs returns to high. the wdqs signal can only transition when data is applied at the chip input and during pre- and postambles. t dqss is the time between wr command and first valid rising edge of wdqs. nominal case is when wdqs edges are aligned with edges of external clk. minimum and maximum values of t dqss define early and late wdqs operati on. any input data will be ignored before the first valid rising wdqs transition. t dqsl and t dqsh define the width of low and high phase of wdqs. the sum of t dqsl and t dqsh has to be t ck . don't care clk# clk t ch t cl t ck cmd, addr, cke t ih t is t ipw clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 ca ba ca: column addres ba: bank address don't care a0, a1 a10-a11 a8 ap ap: autoprecharge cs# data sheet 45 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description back to back wr commands are possible and produce a continuous flow of input data. there must be one nop cycle between two back to back wr commands. any wr burst may be followed by a subsequent rd command. figure 31 shows the timing requirements for a wr followed by a rd. a wr may also be followed by a pre command to the same bank. t wr has to be met as shown in figure 34 . setup and hold time for in coming dqs and dms relative to the wdqs edges are specified as t ds and t dh . dq and dm input pulse width for each input is defined as t dipw . the input data is masked if the corresponding dm signal is high. all timing parameters are defined with graphics dram terminations on. figure 26 basic write burst / dm timing note: wdqs can only transition when data is applied at the chip input and during pre- and postambles. table 20 mapping of wdqs and dm signals wdqs data mask signal controlled dqs wdqs0 dm0 dq0 - dq7 wdqs1 dm1 dq8 - dq15 wdqs2 dm2 dq16 - dq23 wdqs3 dm3 dq24 - dq31 dq t dh dmx dmx: represents one dm line don't care t dh t ds t dh t ds data masked data masked d0 d1 d2 d3 clk# clk t wpre t wpst t dqss nominal preamble postamble min(t dqss ) max(t dqss ) t dqss t ds t dqsl t dqsh t dqsh t dipw t dipw nominal wdqs late wdqs early wdqs wdqs wdqs wdqs hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 46 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.6.2 write - basic sequence figure 27 write basic sequence 1. shown with nominal value of t dqss . 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles. 3. when nops are applied on the command bus, the wdqs and the dq busses remain stable high. 4. when dess are applied on the command bus, the status of the wdqs and dq busses is unknown. clk# clk wr des des com. n/d des des des des 01234567 8 b/c addr. wl = 3 des dq wdqs wl = 4 wdqs dq d0 d3 d2 d1 d0 d3 d2 d1 wr nop nop com. n/d nop nop nop nop b/c addr. wl = 3 nop dq wl = 4 wdqs dq d0 d3 d2 d1 d0 d3 d2 d1 wr: write d#: data to b / c b / c: bank / column address com.: command addr.: address b / c wl: write latency don't care nop: no operation des: deselect n/p: nop or des data sheet 47 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.6.3 write - consecutive bursts 4.6.3.1 gapless bursts figure 28 gapless write bursts 1. shown with nominal value of t dqss . 2. the second wr command may be either for the same bank or another bank. 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles. clk# clk wr n/d des com. n/d des des des des 01234567 8 b/cx addr. wr 9 des b/cy wl = 3 dq wdqs wl = 4 dq wdqs b / cx: bank / column address x dx#: data to b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data to b / cy wl: write latency dx2 dx1 dx3 dx0 dy3 dy0 dy1 dy2 dx2 dx1 dx3 dx0 dy3 dy0 dy1 dy2 don't care wr: write des: deselect n/d: nop / deselect hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 48 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.6.3.2 bursts with gaps figure 29 consecutive write bursts with gaps 1. shown with nominal value of t dqss . 2. the second wr command may be either for the same bank or another bank. 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles. clk# clk wr n/d com . n/d des des des des 01234567 8 b/cx addr. b/cy 9 wr n/d wdqs dq wl = 3 dq wl = 4 wdqs b / cx: bank / column address x wr: write dx#: data to b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data to b / cy wl: write latency dx1 dx2 dy1 dy2 dx3 dx0 dy0 dy3 dx1 dx2 dy1 dy2 dx3 dx0 dy0 dy3 10 des des don't care des: deselect n/d: nop / deselect data sheet 49 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.6.4 write with autoprecharge figure 30 write with autoprecharge 1. shown with nominal value of t dqss . 2. t wr/a starts at the first rising edge of clk after the last va lid edge of wdqs. 3. t rp starts after t wr/a has been expired. 4. when issuing a wr/a command please consider that the t ras requirement also must be met at the beginning of t rp . 5. t wr/a * t cyc t wr . 6. wdqs can only transition when data is applied at the chip input and during pre- and postambles. 012345678 don't care wr/a: write with auto-precharge d#: data to b / c com.: command addr.: address b / c b / c: bank / column address wl: write latency clk# clk wr/a des des com. n/d des des des b/c a9, a7-a2 des des des des a8 910 wl = 3 wdqs t wr/a =4 dq begin of autoprecharge t ras min satisfied wl = 4 wdqs dq t wr/a =4 begin of autoprecharge t ras min satisfied t rp d0 d3 d2 d1 d0 d3 d2 d1 t rp des: deselect n/d: nop or deselect des 11 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 50 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.6.5 write followed by read figure 31 write followed by read 1. shown with nominal value of t dqss . 2. the rd command may be either for the same bank or another bank. 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles. wl = 3 dq t wtr wdqs clk# clk 0123 4567 8 9 wr des des n/d des des b/c b/c des rd n/d don't care wr: write d#: data to b / cx com.: command addr.: address b / c b / c: bank / column address wl: write latency rd: read wdqs wl = 4 dq t wtr wr des des n/d des des des b/c b/c des rd d0 d3 d2 d1 d0 d3 d2 d1 des des des: deselect n/d: nop / deselect data sheet 51 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.6.6 write followed by dterdis figure 32 write command followed by dterdis 1. shown with nominal value of t dqss . 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles. 3. a margin of one clock has been introduc ed in order to make su re that the data termina tion are still on when the last write data reaches the memory. 4. the minimum distance between wr ite and dterdis is one clock. wl = 3 dq wdqs clk# clk 0 12 3456 7 8 9 wr des des des des b/c des des don't care wr: write d#: data to b / cx com.: command addr.: address b / c b / c: bank / column address wl: write latency dtd: dterdis wdqs wl = 4 dq wr des des n/d des des b/c des d0 d3 d2 d1 d0 d3 d2 d1 des des cl = 7 des des dtd cl = 7 cl: cas latency data termination off dtd des: deselect n/d: nop or deselect 10 des des hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 52 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.6.7 write with autoprecharge followed by read / read with autoprecharge figure 33 write with autoprecharge followed by read or read with autoprecharge on another bank. 1. shown with nominal value of t dqss . 2. the rd command is only allowe d for another activated bank. 3. t wr/a is set to 4 in this example. 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles. wr/a: write with autoprecharge b / c: bank / column address rd rd/a: read or read with autoprecharge don't care d#: data to b / cx com.: command addr.: address b / c wl: write latency 0: rd, 1: rd/a dq wl = 3 wdqs t wtr t wr/a t rp dq wl = 4 wdqs t wtr t wr/a t rp wr/a des des n/d des des des b/c b/c des des a8 rd rd/a a9, a2-a7 com. wr/a des des n/d des des des b/c b/c des a8 rd rd/a a9, a2-a7 com. d0 d3 d2 d1 begin of autoprecharge des d0 d3 d2 d1 begin of autoprecharge des: deselect n/d: nop or deselect des clk# clk 01234567 8 9 10 des data sheet 53 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.6.8 write followed by precharge on same bank. figure 34 write followed by precharge on same bank 1. shown with nominal value of t dqss . 2. wr and pre commands are to same bank. 3. t ras requirement must also be met before issuing pre command. 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles. dq wdqs wl = 3 t wr don't care wr: write dx#: data to b / cx com.: command addr.: address b / c b / c: bank / column address dy#: data to b / cy wl: write latency pre: precharge wr des des n/d des des des b/c des pre b des wr des des n/d des des des b/c des pre b des dq wdqs wl = 4 d0 d3 d2 d1 d0 d3 d2 d1 t wr des t rp t rp des n/d: nop or deselect des: deselect clk# clk 012 345 67 8 9 10 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 54 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.7 reads (rd) 4.7.1 read - basic information figure 35 read command read bursts are initiated with a rd command, as shown in figure 35 . the column and bank addresses are provided with the rd command and autoprecharge is either enabled or disabled for that access. the length of the burst initiated with a rd command is 4 or 8. there is no interruption of rd bursts. the two least significant start address bits are ?don?t care?. if autoprecharge is enabl ed, the row being accessed will start precharge at the comp letion of the burst. the begin of the internal autopr echarge will always be one cycle after t ras(min) is met. during rd bursts the memory device drives the read data edge aligned with the rdqs signal which is also driven by the memory. after a programmable cas latency of 7, 8, 9, 10 and 11 the data is driven to the controller. rdqs leaves high state one cycle before its first rising edge (rd preamble t rpre ). after the last falling edge of rdqs a postamble of t rpst is performed. t ac is the time between the positive edge of clk and the appearance of the corresponding driven read data. the skew between rdqs and the crossing point of clk/clk is specified as t dqsck . t ac and t dqsck are defined relatively to the positive edge of clk. t dqsq is the skew between a rdqs edge and the last valid data edge belonging to the rdqs edge. t dqsq is derived at each rdqs edge and begins with rdqs transition and ends with the last valid transition of dqs. t qhs is the data hold skew factor and t qh is the time from the first valid rising edge of rdqs to the first conforming dq going non-valid and it depends on thp and t qhs . thp is the minimum of t cl and t ch . t qhs is effectively the time from the first data transition (before rdqs) to the rdqs transition. the data valid window is derived for each rdqs transition and is defined as t qh minus t dqsq . after completion of a burst, assuming no other commands have been initia ted, data will go high and rdqs will go high. back to back rd commands are possible producing a continuous flow of output data. there has to be one nop cycle between back to back rd commands. any rd burst may be followed by a subsequent wr command. the minimum required number of nop commands between the rd command and the wr command ( t rtw ) depends on the programmed read latency and the programmed write latency t rtw (min)= (cl+4-wl). chapter 4.7.7 shows the timing requirements for rd followed by a wr with some combinations of cl and wl. a rd may also be followed by a pre command. since no interruption of bursts is allowed the minimum time between a rd command and a pre is two clock cycles as shown in chapter 4.7.8 . all timing parameters are defined with controller terminations on. clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 ca ba ca: column addres ba: bank address don't care a0, a1 a10-a11 a8 ap ap: autoprecharge cs# data sheet 55 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description figure 36 basic read burst timing 1. the gddr3 sgram switches off the dq terminations one cycle before data appears on the bus and drives the data bus high. 2. the gddr3 sgram drives the data bus high one cycle after the last data driven on the bus before switching the termination on again. t rpst rdqs don't care all dqs collectively clk# clk t ch t cl t qh t dqsq t dqsck t ac t rpre t ck t hp t dqsq t qhs dq (first data valid) dq (last data valid) d0 d1 d2 d3 data valid window t lz t hz d0 d1 d2 d3 d0 d1 d2 d3 hi-z : not driven by ddriii sgram preamble postamble hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 56 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.7.2 read - basic sequence figure 37 read burst 1. shown with nominal t ac and t dqsq . 2. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. 3. the dq terminations are switched off 1 cycle before th e first read data and on again 1 cycle after the last read data. clk# clk rd n/d n/d com. n/d n/d n/d n/d n/d 01 2 367 8 b / c addr. cas latency = 8 rdqs dq cas latency = 7 rdqs dq don't care n/d 9 d3 d2 d1 d0 d3 d2 d1 d0 b / c: bank / column address rd: read dx: data from b / c com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d: nop or deselect 10 11 n/d data sheet 57 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.7.3 consecutive read bursts 4.7.3.1 gapless bursts figure 38 gapless consecutive read bursts 1. the second rd command may be either for the same bank or another bank. 2. shown with nominal t ac and t dqsq . 3. example applies only when read commands are issued to same device. 4. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. 5. the dq terminations are switched off 1 cycle before th e first read data and on again 1 cycle after the last read data. clk# clk n/d n/d com. n/d n/d n/d 2367 8 b/cx addr. 9 cas latency = 8 rdqs rdqs dq dq dx2 dx1 dx3 dy0 dy1 dy2 dy3 dx0 cas latency = 7 don't care 10 dx2 dx1 dx3 dy0 dy1 dy2 dy3 dx0 n/d n/d 11 b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data from b / cy dqs : terminations off rdqs : not driven 01 rd n/d n/d n/d rd n/d: nop or deselect b/cy 12 13 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 58 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.7.4 bursts with gaps figure 39 consecutive read bursts with gaps 1. the second rd command may be either for the same bank or another bank. 2. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. 3. the dq terminations are switched off 1 cycle before th e first read data and on again 1 cycle after the last read data. clk# clk rd n/d n/d com. n/d n/d n/d n/d n/d 012 3 b/cx addr. rd b/cy cas latency = 7 cas latency = 8 rdqs rdqs dq dq n/d n/d dx0 dx1 dx2 dx3 dy0 dy1 dy2 dy3 dx0 dx1 dx2 dx3 dy0 dy1 dy2 don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data from b / cy 6 7 8 9 10 11 12 dqs : terminations off rdqs : not driven data sheet 59 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.7.5 read followed by dterdis figure 40 read command followed by dterdis 1. at least 3 nops are required between a read command and a dterdis command in order to avoid contention on the rdqs bus in a 2 rank system. 2. cas latency 7 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of 4 clocks. 4. the dashed lines (rdqs bus) describe the rdqs beh avior in the case where the dterdis command corresponds to a read command ap plied to the second graphics dram in a 2 rank system. in this case, rdqs would be driven by the second graphics dram. clk# clk rd n/d com. n/d n/d n/d n/d n/d 012367 8 b/cx addr. 9 cas latency = 7 10 n/d n/d don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d n/d 12 13 n/d dtd rdqs dq dx0 dx1 dx2 dx3 rd n/d com. n/d n/d n/d n/d b/cx addr. cas latency = 7 n/d n/d n/d n/d n/d rdqs dq dx0 dx1 dx2 dx3 dtd n/d n/d n/d 14 dtd: dterdis des: deselect n/d: nop or deselect 15 16 clk# clk 012367 8 9 10 13 14 15 16 17 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 60 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.7.6 read with autoprecharge figure 41 read with autoprecharge 1. when issuing a rd/a command, the t ras requirement must be met at the beginning of autoprecharge 2. shown with nominal t ac and t dqsq 3. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. 4. the dq terminations are switched off 1 cycle before th e first read data and on again 1 cycle after the last read data. 5. t ras lockout support. clk# clk rd/a n/d n/d com. n/d n/d n/d n/d n/d n/d 012367 8 a8 b / c a9, a7-a2 cas latency = 8 dq cas latency = 7 dq rdqs rdqs d3 d2 d1 d0 d3 d2 d1 d0 bl / 2 t rp begin of autoprecharge don't care rd/a: read with auto-precharge b / c: bank / column address dx: data from b / c com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d: nop or deselect 910 data sheet 61 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.7.7 read followed by write figure 42 read followed by write 1. shown with nominal t ac , t dqsq and t dqss 2. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. 3. the dq terminations are switched off 1 cycle before th e first read data and on again 1 cycle after the last read data 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles. 5. the write command may be either on the same bank or on another bank. clk# clk com. 012367 8 addr. 9 10 don't care 11 rd des des des des b/cr des des rd des des des des b/cr des des des cas latency = 7 t rtw write latency = 3 wdqs rdqs dq cas latency = 8 t rtw write latency = 4 wdqs rdqs dq d3r d2r d1r d0r des wr b/cw d3w d2w d1w d0w d3r d2r d1r d0r d2w d1w d0w des b/cw wr dxr: read data from b / c com.: command addr.: address b / c dxw: write data from b / c b / cw: bank / column address for write b / cr: bank / column address for read rd: read wr: write dqs : terminations off rdqs : not driven des des des des des des: deselect 12 13 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 62 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.7.8 read followed by precharge on the same bank figure 43 read followed by precharge on the same bank 1. t ras requirement must also be met before issuing pre command 2. rd and pre commands are applied to the same bank. 3. shown with nominal t ac and t dqsq 4. rdqs will start driving high 1/2 cycl e prior to the first falling edge and st op 1/2 cycle after the last rising edge of rdqs. clk# clk rd n/d n/d com. n/d pre n/d n/d n/d n/d 01 2367 8 b / c addr. don't care cas latency = 8 rdqs dq cas latency = 7 rdqs dq d3 d2 d1 d0 d3 d2 d1 d0 t rp b / c: bank / column address rd: read dx: data from b / c com.: command addr.: address b / c pre: precharge dqs : terminations off rdqs : not driven n/d: nop or deselect 910 data sheet 63 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.8 data termination disable (dterdis) figure 44 data terminal disable command the data termination disable command is detected by the device by snooping the bus for read commands when cs is high. the terminator s are disabled starting at cl - 1 clocks after the dterdis command is detected and the duration is 4 clocks. the command and address terminators are always enabled. dterdis may only be applied to the gddr3 graphics memory if it is not in th e power down or in the self refresh state. the timing relationship between dterdis and other commands is defined by th e constraint to avoid contention on the rdqs bu s (i.e read to dterdis transition) or the necessity to have a defined termination on the data bus during write (i.e. write to dterdis transition). act and pre/preall may be applied at any time before or after a dterdis command. figure 45 dterdis timing clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 don't care a0, a1 a10-a11 a8 ap: autoprecharg e cs# clk# clk dtd n/d n/d com. n/d n/d n/d n/d n/d 01 2 367 8 addr. cas latency = 7 don't care dtd: dterdis com.: command addr.: address b / c 9 n/d n/d data terminations are disabled dq termination n/d : nop or desele c 10 11 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 64 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.8.1 dterdis followed by dterdis figure 46 dterdis command followed by dterdis 1. at least 1nop is required between 2 dterdis commands . this correspond to a r ead to read transition on the other memory in a 2 rank system. 2. cas latency 7 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of 4 clocks. 4. the dashed lines (rdqs bus) describe the rdqs beh avior in the case where the dterdis command corresponds to a read command ap plied to the second graphics dram in a 2 rank system. in this case, rdqs would be driven by the second graphics dram. clk# clk com. n/d n/d n/d n/d n/d 012367 8 addr. 9 cas latency = 7 10 n/d n/d n/d n/d 11 12 n/d rdqs dq dtd com. n/d n/d n/d n/d addr. cas latency = 7 n/d n/d n/d n/d n/d rdqs dq dtd n/d n/d n/d 13 dtd dtd n/d n/d com. n/d n/d n/d n/d addr. cas latency = 7 n/d n/d n/d n/d rdqs dq dtd n/d n/d n/d don't care b / cx: bank / column address x rd: read n/d : nop or deselect com.: command addr.: address b / c dqs : terminations off rdqs : not driven dtd: dterdis dx#: data from b / cx 14 15 clk# clk 03456789101112131415 n/d n/d data sheet 65 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.8.2 dterdis followed by read figure 47 dterdis command followed by read 1. at least 3 nops are required between a dterdis command and a read command in order to avoid contention on the rdqs bus in a 2 rank system. 2. cas latency 7 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of 4 clocks. clk# clk n/d com. n/d n/d n/d n/d n/d 012 56789 addr. cas latency = 7 12 n/d n/d don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d n/d 13 14 n/d rdqs dq n/d com. n/d n/d n/d n/d addr. cas latency = 7 n/d n/d n/d n/d n/d rdqs dq dtd n/d n/d n/d 15 dtd: dterdis dx0 dx1 dx2 dx3 rd dtd rd dx0 dx1 dx2 dx3 b/cx b/cx n/d: nop or deselect 16 17 hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 66 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.8.3 dterdis followed by write figure 48 dterdis command followed by write 1. write shown with nominal value of t dqss . 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles 3. the minimum distance between dterdis and write is (cl - wl + bl/2 +2) clocks. clk# clk com. 01236789 10 addr. 11 12 don't care 13 des des des des des des des des des des des des cas latency = 7 write latency = 3 wdqs dq cas latency = 8 write latency = 4 wdqs dq des wr b/cw d3w d2w d1w d0w des b/cw wr com.: command addr.: address b / c dxw: write data from b / c b / cw: bank / column address for write wr: write dqs : terminations off dtd dtd d2w d1w d0w dtd: dterdis des des des des des des des: deselect data sheet 67 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.9 precharge (pre/preall) figure 49 precharge command the precharge command is used to deactivate the open row in a particular bank (pre) or the open rows in all banks (preall). the bank(s) will enter the idle state and be available again for a new row access after the time t rp . a8/ap sampled with the pre command determines whether one or all banks are to be precharged. for pre commands ba0, ba1 select the bank. for preall inputs ba0, ba1 are ?don?t care?. the pre/preall command may not be given unless the t ras requirement is met for the selected bank (pre), or for all banks (preall). clk# clk ras# cke cas# we# a0-7,9-11 ba0-ba1 ba ba: bank address don't care a8 all all: high selects all banks cs# low selects bank ba table 21 ba1 and ba0 precharge bank selection a8 / ap ba1 ba0 precharged bank(s) 0 0 0 bank 0 only 0 0 1 bank 1 only 0 1 0 bank 2 only 0 1 1 bank 3 only 1 x x all banks hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 68 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 50 precharge timing clk# clk act pre nop act nop row row b.x b.x b.x t ras t rp command a0 - a11 ba0 - ba1 nop t rc row: row addres s don't care b.x: bank x act: activate pre: precharge data sheet 69 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.10 auto refresh command (aref) figure 51 auto refresh command aref is used to do a refresh cycle on one row in each bank. the addresses are generated by an internal refresh controller; external address pins are ?don?t care?. all banks must be idle before the aref command can be applied. the delay between the aref command and the next act or subsequent aref must be at least t rfc (min). the refresh period starts when the aref command is entered and ends t rfc later at which time all b anks will be in the idle state. within a period of t ref the whole memory has to be refreshed. the average periodic interval time from aref to aref is then t refi . to improve efficiency bursts of aref commands can be used. such bursts may consist of maximum 8 aref commands. t rfc (min) is the minimum required time between two aref commands inside of one aref burst. according to the number of aref commands in one burst the average required time from one aref burst to the next can be increased. example: if the aref bursts consists of 8 aref commands, the average time from one aref burst to the next is 8* t refi . the aref command generates an update of the ocd output impedance and of the addresses, commands and dq terminations. the timing parameter t ko (see chapter 4.2.2 must be met. figure 52 auto refresh cycle clk# clk ras# cke cas# we# a0-a11 ba0-ba1 ba: bank addres s don't care cs# clk# clk arf nop t rp t rfc command pre cke nop nop a.c. arf t refi don't care arf: auto refresh a.c.: aref or act command hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 70 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.11 self-refresh 4.11.1 self-refresh entry (srefen) the self-refresh mode can be used to retain data in the gddr3 graphics ram even if the rest of the system is powered down. when in the self-refresh mode, the gddr3 graphics ram retains data without external clocking. the self-refresh command is initiated like an auto-ref resh command except cke is disabled (low). self refresh entry is only possible if all banks are precharged and t rp is met. the gddr3 graphics ram has a build-in timer to accommodate self-refresh operation. the self- refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the has entered the self-refresh mode, all external control signals, ex cept cke are disabled. the address, command and data terminators remain on. the dll and the clock are internally disabled to save power. the user may halt the external clock while the device is in self-refresh mode the next clock after self- refresh entry, however the clock must be restarted before the device can exit self-refresh operation. figure 53 self-refresh entry command figure 54 self refresh entry clk# clk ras# cke cas# we# a0-a7 ba0-ba1 don't car e a9-a11 a8 cs# clk# clk don't care command cke pa.: precharge all command (or last of pres to each bank) srf: self refresh command t rp pa aref clk/clk# may be halted 1 clock data sheet 71 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.12 self-refresh exit (srefex) figure 55 self refresh exit command to exit the self refresh mo de, a stable external clock is needed before setting cke high asynchronously. once the self-refresh exit command is registered, a delay equal or longer than t xsc must be satisfied before any command can be applied. during this time, the dll is automatically enabled, reset and calibrated. cke must remain high for the entire self-refresh exit period and commands must be gated off with cs held high. alternately, nop commands may be registered on each positive clock edge during the self refresh exit interval. figure 56 self refresh exit clk# clk ras# cke cas# we# a0-a11 don't care a9-a11 cs# clk# clk don't care n / d t xsc command cke a.c. a.c.: any command n / d: nop or desel command n / d n / d clk, clk# must be stable hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 72 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.13 power-down figure 57 power down command the requires cke to be active at all times an access is in progress: from the issuing of a read or write command until completion of the burst. for reads, a burst completion is defined after the rising edge of the read postamble. for writes, a burst completion is defined one clock after the rising edge of the write postamble. for read with autoprecharge and write with autoprecharge, the intern al autoprecharge must be completed before entering power-down. power-down is entered when cke is registered low. (no access can be in progress. "access" means as well read or write to a second memory sharing the data bus in a dual rank system.) if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk, clk and cke. for maximum power saving, the user has the option of disabling the dll prior to entering power- down. in that case the dll must be enabled and reset after exiting power-down, and 1000 cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the gddr3 graphics ram, all the othe r input signals are ?don?t care?. power down duration is limited by the refresh requirements of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or desel command). a valid executable command may be applied t xpn later. figure 58 power-down mode clk# clk ras# cke cas# we# ba0-ba1 don't care a0-a11 cs# 1 2 1: desel, 2: no p clk# clk n / d: nop or deselect command don't care a.c. t xpn comm. n / d cke a.c.: any command a.c. power-down mode entry power-down mode exit t is n / d n / d n / d data sheet 73 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description 4.14 dll off mode the hyb18h256321afl14/16/20 supports for very low frequency operation the dll off mode. entering this mode requires an extended mode register set command disabling the dll by setting a6 to 1. for 350 mhz clock speed and faster dll on mode operation is recommended. most of the commands and timings described in chapter 4.5 to chapter 4.13 are also applicable for dll off mode. differences exist for the frequency range, th e initialization and the timing of wr command and rd command. 4.14.1 frequency rang e in dll off mode operations in dll off mode are limited to the frequencies between 100 mhz and 350 mhz. 4.14.2 initializati on in dll off mode figure 59 dll off: power up sequence table 22 dll off: general timing parameter for hyb18h256321afl14/16/20 parameter read latency symbol limit values unit note ?14 ?16 ?20 min max min max min max clock dll off mode system frequency 9 f ck9 100 350 100 350 100 350 mhz 8 f ck8 100 350 100 350 100 350 mhz 7 f ck7 100 350 100 350 100 350 mhz clk# clk cke min. 200 s com. vdd vddq vref res t ats t ath pa emr t rp mrs t mrd arf a.c. arf pa t rfc t rfc t rp cycles min. 300 vdd and clk stable don't care pa: preall command a.c.: any command arf: auto refresh command t mrd cycles min. 700 des des a6 mrs: mrs command emr: emrs command des : deselect hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 74 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.14.3 writes (wr) in dll off mode figure 60 dll off: write followed by read table 23 general timing paramete r for hyb18h256321afl14/16/20 parameter symbol limit values unit ?14 ?16 ?20 min max min max min max write comm. to the first dqs latching transition t dqss (wl* t ck ) - 0.5 (wl* t ck ) + 0.5 (wl* t ck ) - 0.5 (wl* t ck ) + 0.5 (wl* t ck ) - 0.5 (wl* t ck ) + 0.5 ns data-in and dm input pulse width (each input) t dipw 0.77 ? 0.77 ? 0.88 ? ns dqs write preamble time t wpre 0.55 ? 0.55 ? 0.63 ? ns dqs write postamble time t wpst 0.88 1.32 0.88 1.32 1.0 1.5 ns write to read t wtr 8?8?8? ns write recovery time t wr 14 ? 14 ? 14 ? ns # , + # , + 7 2 $ % 3 # o m $ % 3 ! d d r $ % 3 " # " # $ % 3 $ % 3 $ % 3 $ o n g t # a r e $ % 3 2 $ t 7 4 2 7 , 7 $ 1 3 # ! 3 l a t e n c y $ 1 7 , 7 $ 1 3 $ 1 t 7 4 2 # ! 3 l a t e n c y 7 2 $ % 3 $ % 3 $ % 3 $ % 3 " # $ % 3 $ % 3 2 $ $ % 3 $ % 3 $ % 3 $ % 3 $ % 3 t $ 1 3 # + / & & 2 $ 1 3 $ $ $ $ 2 $ 1 3 $ $ $ $ t $ 1 3 # + / & & t ! # / & & $ $ 1 s 4 e r m i n a t i o n s o f f 2 $ 1 3 . o t d r i v e n $ $ a t a t o " # x # o m # o m m a n d ! d d r ! d d r e s s " # 7 , 7 r i t e , a t e n c y 7 2 7 2 ) 4 % " # " a n k # o l u m n a d d r e s s 2 $ 2 % ! $ $ $ $ t ! # / & & $ % 3 $ % 3 $ % 3 $ e s e l e c t $ % 3 $ % 3 " # $ % 3 $ % 3 data sheet 75 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description figure 61 write followed by precharge 4.14.4 reads (rd) in dll off mode definition of read latency in dll off mode is different from dll on mode. since in dll off mode the read data is not synchronized to the clk, the internal access time to the memory array becomes visible. read data in dll off mode appears on the i/o balls after (cl - 1) + t ac . cl is the value for the read latency which is set in the mode register. clk# clk wr des com. des des 01234567 8 addr. des b/c 9 des pre b des des des wr des des des des des des b/c des des pre b wr des des des des des des b/c des des pre b dq wl = 3 wdqs t rp t wr dq wl = 4 wdqs t rp t wr d0 d3 d2 d1 d0 d3 d2 d1 don't care com.: command addr.: address b / c wl: write latency wr: write dx#: data to b / cx b / c: bank / column address dy#: data to b / cy pre: precharge des: deselect com. contin. addr. contin. hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 76 rev. 1.03, 2005-12 06302005-ses0-fm0m figure 62 dll off: read burst table 24 read timing parameter for hyb18h256321afl14/16/20 parameter read latency symbol limit values unit note ?14 ?16 ?20 min max min max min max read to write command delay t rtw t rtw(min) = (cl+4-wl) t ck read cycle timing parameters for data and data strobe data access time from clock in dll off mode t acoff 2.4 6.2 2.4 6.2 2.4 6.2 ns dqs edge to clock edge skew in dll off mode t dqsck 2.4 6.2 2.4 6.2 2.4 6.2 ns clk# clk rd n/d n/d com. n/d n/d n/d n/d n/d n/d 01 2367 8 9 10 b / c addr. cas latency = 7 cas latency = 8 rdqs dq dq b / c: bank / column address don't care rd: read dx: data from b / c com.: command addr.: address b / c t acoff t dqsck t acoff t dqsck rdqs d0 d3 d2 d1 d0 d3 d2 d1 n/d: nop or deselect data sheet 77 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 functional description figure 63 dll off: read followed by write clk# clk com. 01236789 10 cas latency = 7 addr. 11 12 rd des des des des b/cr des t rtw t dqsckoff don't care t acoff rdqs wdqs cas latency = 8 rd des des des des b/cr des des t rtw t dqsckoff rdqs wdqs dq dq 13 d0r d3r d2r d1r d0w d2w d1w d0r d3r d2r d1r d0w wr des b/cw des wr b/cw write latency = 4 write latency = 3 t acoff dxr: read data from b / c com.: command addr.: address b / c dxw: write data from b / c b / cw: bank / column address for write b / cr: bank / column address for read rd: read wr: write dqs : terminations off rdqs : not driven d0w des d1w d2w des des des des des: deselect des des hyb18h256321af[l] 256-mbit gddr3 functional description data sheet 78 rev. 1.03, 2005-12 06302005-ses0-fm0m 4.14.5 self refresh in dll off mode self refresh in dll off mode is basically the same like in dll on mode. table 25 self refresh exit timing parameter for hyb18h256321afl14/16/20 parameter read latency symbol limit values unit note ?14 ?16 ?20 min max min max min max self refresh exit time t xsc 700 ? 700 ? 700 ? t ck data sheet 79 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5 electrical characteristics 5.1 absolute maximum ratings and operation conditions stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only, and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this spec ification is not implied. ex posure to absolute maximum rating conditions for extended periods may a ffect device reliability. table 26 absolute maximum ratings parameter symbol rating unit min. max. power supply voltage v dd -0.5 2.5 v power supply voltage for output buffer v ddq -0.5 2.5 v input voltage v in -0.5 2 .5 v output voltage v out -0.5 2 .5 v storage temperature t stg -55 +150 c junction temperature t j +125 c short circuit output current i out ?50ma hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 80 rev. 1.03, 2005-12 06302005-ses0-fm0m 5.2 dc operation conditions 5.2.1 recommended power & dc operation conditions. table 27 power & dc operation conditions.(0 c t c 85 c) parameter symbol limit values unit note s min. typ. max. power supply voltage v dd , v dda 1.9 2.0 2.1 v 1)2) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. power supply voltage for i/o buffer v ddq 1.9 2.0 2.1 v 1)2) 2) hyb18h256321af?12/14/16 power supply voltage v dd , v dda 1.7 1.8 1.9 v 1)3) 3) hyb18h256321afl14/16/20 power supply voltage for i/o buffer v ddq 1.7 1.8 1.9 v 1)3) reference voltage v ref 0.69* v ddq ?0.71* v ddq v 4) 4) v ref is expected to equal 70% of v ddq for the transmitting device and to tr ack variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% v ref (dc). thus, from 70% of v ddq , v ref is allowed 19mv for dc error and an additional 27mv for ac noise. output low voltage v ol(dc) ??0.8v input leakage current i il ?5.0 ? +5.0 a 5) 5) i il and i ol are measured with odt disabled. clk input leakage current i ilc ?5.0 ? +5.0 a output leakage current i ol ?5.0 ? +5.0 a 5) data sheet 81 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.3 dc & ac logic input levels 5.4 differential clo ck dc and ac levels table 28 dc & ac logic input levels (0 c t c 85 c) parameter symbol limit values unit notes min. max. input logic high voltage, dc v ih (dc) v ref + 0.15 ? v 1) 1) the dc values define where the input slew rate requ irements are imposed, and the input signal must not violate these levels in orde r to maintain a valid level. input logic low voltage, dc v il (dc) ? v ref -0.15 v 1) input logic high voltage, ac v ih (ac) v ref + 0.25 ? v 2)3) 2) input slew rate = 3v/ns. if the input slew rate is less than 3v/ns, input timing ma y be compromised. all slew rates are measured between v il (dc) and v ih (dc). 3) v ih overshoot: v ih (max) = v ddq +0.5v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = 0v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. input logic low voltage, ac v il (ac) ? v ref - 0.25 v 2)3) input logic high, dc, reset pin v ihr (dc) 0.65 v ddq v ddq + 0.3 v input logic low, dc, reset pin v ilr (dc) -0.3 0.35 v ddq v input logic high, dc, mf pin v ihmf (dc) v dd v dd + 0.3 v 4) 4) the mf pin must be hard-wired on board to either v dd or v ss . input logic low,dc, mf pin v ilmf (dc) ?0.3 0 v table 29 differential clock dc and ac input conditions (0 c t c 85 c) parameter symbol limit values unit notes min. max. clock input mid-point voltage, clk and clk v mp(dc) 0.7 v ddq ? 0.10 0.7 v ddq + 0.10 v 1) 1) all voltages referenced to v ss. clock input voltage level, clk and clk v in(dc) 0.42 v ddq + 0.3 v 1) clock dc input differential voltage, clk and clk v id(dc) 0.3 v ddq v 1) clock ac input differential voltage, clk and clk v id(ac) 0.5 v ddq + 0.5 v 1)2) 2) v id is the magnitude of the difference between the input level on clk and the input level on clk . ac differential crossing point input voltage v ix(ac) 0.7 v ddq ? 0.15 0.7 v ddq + 0.15 v 1)3) 3) the value of v ix is expected to equal 0.7 v ddq of the transmitting device and must track variations in the dc level of the same. hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 82 rev. 1.03, 2005-12 06302005-ses0-fm0m 5.5 output t est conditions figure 64 output test circuit 5.6 pin capacitances table 30 pin capacitances (vddq = 1.8v, ta = 25c, f= 1mhz) parameter symbol min max unit notes input capacitance: a0-a11, ba0-2 ,cke, cs , cas , ra s, we , cke, res,clk,clk ci,cck 1.5 2.5 pf input capacitance: dq0-dq31, rdqs0-rdqs3, wdqs0-wdqs3, dm0- dm3 cio 2.5 3.5 pf dq 60 ohm test point dqs v ddq data sheet 83 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.7 driver current characteristics 5.7.1 driver iv char acteristics at 40 ohms figure 65 represents the driver pu ll-down and pull-up iv characteristics under process, voltage and temperature best and worst case conditions. the actual driver pu ll-down and pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ? , setting the nominal driver output impedance to 40 ? . figure 65 40 ohm driver pull-down and pull-up characteristics table 31 lists the numerical values of the minimum and ma ximum allowed values of the output driver pull-down and pull-up iv characteristics. table 31 programmed driver iv characteristics at 40 ohm voltage (v) pull-down current (ma) pull-up current (ma) minimum maximum minimum maximum 0.1 2.32 3.04 -2.44 -3.27 0.2 4.56 5.98 -4.79 -6.42 0.3 6.69 8.82 -7.03 -9.45 0.4 8.74 11.56 -9.18 -12.37 0.5 10.70 14.19 -11.23 -15.17 0.6 12.56 16.72 -13.17 -17.83 0.7 14.34 19.14 -15.01 -20.37 0.8 16.01 21.44 -16.74 -22.78 0.9 17.61 23.61 -18.37 -25.04 1.0 19.11 26.10 -19.90 -27.17 1.1 20.53 28.45 .21.34 -29.17 1.2 21.92 30.45 -22.72 -31.25 1.3 23.29 32.73 -24.07 -33.00 1.4 24.65 34.95 -25.40 -35.00 1.5 26.00 37.10 -26.73 -37.00 1.6 27.35 39.15 -28.06 -39.14 1.7 28.70 41.01 -29.37 -41.25 1.8 30.08 42.53 -30.66 -43.29 1.9 ? 43.71 ? -45.23 2.0 ? 44.89 ? -47.07 pull-up characterstics -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0,0 0,5 1,0 1,5 2,0 vddq - vout (v) iout (ma) pull-down characterstics 0 5 10 15 20 25 30 35 40 45 50 0,0 0,5 1,0 1,5 2,0 vout (v) iout (ma) hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 84 rev. 1.03, 2005-12 06302005-ses0-fm0m 5.7.2 termination iv ch aracteristic at 60 ohms figure 66 represents the dq termination pull-up iv characte ristic under process, voltage and temperature best and worst case conditions. the actual dq termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ? , setting the nominal dq termination impedance to 60 ? . (extended mode register programmed to zq/4). figure 66 60 ohm active termination characteristic table 32 lists the numerical values of the minimum and maximu m allowed values of the ou tput driver termination iv characteristic. table 32 programmed terminator characteristics at 60 ohm voltage (v) terminato r pull-up current (ma) voltage (v) terminato r pull-up current (ma) minimum maximum minimum maximum 0.1 -1.63 -2.18 1.1 -14.23 -19.45 0.2 -3.19 -4.28 1.2 -15.14 -20.83 0.3 -4.69 -6.30 1.3 -16.04 -22.00 0.4 -6.12 -8.25 1.4 -16.94 -23.33 0.5 -7.49 -10.11 1.5 -17.82 -24.67 0.6 -8.78 -11.89 1.6 -18.70 -26.09 0.7 -10.01 -13.58 1.7 -19.58 -27.50 0.8 -11.16 -15.19 1.8 -20.44 -28.86 0.9 -12.25 -16.69 1.9 ? -30.15 1.0 -13.27 -18.11 2.0 ? -31.38 60 ohm termination characterstics -35 -30 -25 -20 -15 -10 -5 0 0,0 0,5 1,0 1,5 2,0 vddq - vout (v) iout (ma) data sheet 85 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.8 termination iv char acteristic at 120 ohms figure 67 represents the dq or add/cmd termination pull-up iv characteristic under process, voltage and temperature best and worst case conditions. the actual termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ? , setting the nominal termination impedance to 120 ? . (extended mode register programmed to zq/2 for dq terminations or cke = 0 at the res transition during power-up for add/cm d terminations). figure 67 120 ohm active termination characteristic table 33 lists the numerical values of the minimum and maximum allowed values of the termination iv characteristic. table 33 programmed terminator characteristics of 120 ohm voltage (v) terminato r pull-up current (ma) voltage (v) terminato r pull-up current (ma) minimum maximum minimum maximum 0.1 -0.81 -1.09 1.1 -7.11 -9.72 0.2 -1.60 -2.14 1.2 -7.57 -10.42 0.3 -2.34 -3.15 1.3 -8.02 -11.00 0.4 -3.06 -4.12 1.4 -8.47 -11.67 0.5 -3.74 -5.06 1.5 -8.91 -12.33 0.6 -4.39 -5.94 1.6 -9.35 -13.05 0.7 -5.00 -6.79 1.7 -9.79 -13.75 0.8 -5.58 -7.59 1.8 -10.22 -14.43 0.9 -6.12 -8.35 1.9 ? -15.08 1.0 -6.63 -9.06 2.0 ? -15.69 120 ohm termination characterstics -16 -14 -12 -10 -8 -6 -4 -2 0 0,0 0,5 1,0 1,5 2,0 vddq - vout (v) iout (ma) hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 86 rev. 1.03, 2005-12 06302005-ses0-fm0m 5.9 termination iv char acteristic at 240 ohms figure 68 represents the add/cmd termination pull-up iv char acteristic under process, voltage and temperature best and worst case conditions. the actual add/cmd termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ? , setting the nominal termination impedance to 240 ? . (cke = 1at the res transition during power-up for add/cmd terminations). figure 68 240 ohm active termination characteristic table 34 lists the numerical values of the minimum and ma ximum allowed values of the add/cmd termination iv characteristic. table 34 programmed terminator characteristic at 240 ohm voltage (v) terminato r pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -0.41 -0.55 1.1 -3.56 -4.86 0.2 -0.80 -1.07 1.2 -3.79 -5.21 0.3 -1.17 -1.58 1.3 -4.01 -5.50 0.4 -1.53 -2.06 1.4 -4.23 -5.83 0.5 -1.87 -2.53 1.5 -4.46 -6.17 0.6 -2.20 -2.97 1.6 -4.68 -6.52 0.7 -2.50 -3.40 1.7 -4.90 -6.88 0.8 -2.79 -3.80 1.8 -5.11 -7.21 0.9 -3.06 -4.17 1.9 ? -7.54 1.0 -3.32 -4.53 2.0 ? -7.85 240 ohm termination characterstics -8,0 -7,0 -6,0 -5,0 -4,0 -3,0 -2,0 -1,0 0,0 0,0 0,5 1,0 1,5 2,0 vddq - vout (v) iout (ma) data sheet 87 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.10 operating currents 5.10.1 operating current rati ngs (hyb18h256321af?12/14/16) table 35 operating current ratings (0 c tc 85 c) parameter symbol values unit notes ?12 ?14 ?16 typ. typ. typ. operating current i dd0 500 450 405 ma 1)2)3) 1) idd specifications are tested afte r the device is properly initialized. 2) input slew rate = 3v/ns. 3) measured with output open and on die termination off. operating current i dd1 460 425 380 ma 1)2)3) precharge power-down standby current i dd2p 270 240 215 ma 1)2)3) precharge floating standby current i dd2f 350 320 280 ma 1)2)3) precharge quiet standby current i dd2q 320 290 255 ma 1)2)3) active power-down standby current i dd3p 270 245 215 ma 1)2)3) active standby current i dd3n 455 410 365 ma 1)2)3) operating current burst read i dd4r 805 725 640 ma 1)2)3) operating current burst write i dd4w 640 580 510 ma 1)2)3) auto-refresh current (t rc =min(t rfc )) i dd5b 610 570 520 ma 1)2)3) auto-refresh current at t refi i dd5d 410 365 325 ma 1)2)3) self refresh current i dd6 888ma 1)2)3)4) 4) enables on-chip refresh and address counter. operating current i dd7 630 600 570 ma 1)2)3) hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 88 rev. 1.03, 2005-12 06302005-ses0-fm0m 5.10.2 operating current rati ngs (hyb18h2563 21afl14/16/20) table 36 operating current ratings (0 c tc 85 c) parameter symbol values unit notes ?14 ?16 ?20 typ. typ. typ. operating current i dd0 405 370 330 ma 1)2)3) 1) idd specifications are tested afte r the device is properly initialized. 2) input slew rate = 3v/ns. 3) measured with output open and on die termination off. operating current i dd1 385 345 315 ma 1)2)3) precharge power-down standby current i dd2p 220 190 170 ma 1)2)3) precharge floating standby current i dd2f 285 250 220 ma 1)2)3) precharge quiet standby current i dd2q 260 230 200 ma 1)2)3) active power-down standby current i dd3p 220 195 170 ma 1)2)3) active standby current i dd3n 370 330 285 ma 1)2)3) operating current burst read i dd4r 650 610 500 ma 1)2)3) operating current burst write i dd4w 520 465 400 ma 1)2)3) auto-refresh current (t rc =min(t rfc )) i dd5b 535 490 405 ma 1)2)3) auto-refresh current at t refi i dd5d 330 290 250 ma 1)2)3) self refresh current i dd6 888ma 1)2)3)4) 4) enables on-chip refresh and address counter. operating current i dd7 550 530 500 ma 1)2)3) data sheet 89 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.11 operating current measurement conditions 1. 0 c tc 85 c 2. data bus consists of dq, dm, wdqs. table 37 operating current measurement conditions symbol parameter/condition i dd0 operating current - one bank, activate - precharge t ck =min( t ck ), t rc =min( t rc ) databus inputs are switching; address and control inputs are switching, cs = high between valid commands. i dd1 operating current - one bank, activate - read - precharge one bank is accessed with t ck =min(t ck ), t rc =min( t rc ), cl = cl(min), address and control inputs are switching; cs = high between valid commands. i out =0ma i dd2p precharge power-down standby current all banks idle, power-down mode, cke is low, t ck =min( t ck ), data bus inputs are stable (high). i dd2f precharge floating standby current all banks idle; cs is high, cke is high, t ck =min( t ck ); address and control inputs are switching; data bus input are stable (high). i dd2q precharge quiet standby current cs is high, all banks idle, cke is high, t ck =min( t ck ), address and other control inputs stable (high), data bus inputs are stable (high). i dd3p active power-down standby current one bank active, cke is low, address and contro l inputs are stabl e (high); data bus inputs are stable (high); standard active power-down mode. i dd3n active standby current one bank active, cs is high, cke is high, t ras = t ras,max , t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd4r operating current - burst read one bank active; continuous read bursts, cl = cl(min); t ck =min( t ck ); t ras = t ras,max ; address and control inputs are switching; iout = 0 ma. i dd4w operating current - burst write one bank active; continuous write bursts; t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd5b burst auto refresh current refresh command at t rfc =min(t rfc ); t ck =min( t ck ); cke is high, cs is high between all valid commands; other command and address inputs ar e switching; data bus inputs are switching. i dd5d distributed auto refresh current t ck = t ckmin ; refresh command every t refi ; cke is high, cs is high between valid commands; other command and address inputs are swit ching; data bus inputs are switching. i dd6 self refresh current cke max( v il ), external clock off, ck and ck low; address and control inputs are stable (high); data bus inputs are stable (high). i dd7 operating bank interleave read current all banks interleaving with cl = cl(min); t rcd = t rcdrd (min); t rrd = t rrd (min); i out =0 ma; address and control inputs are stable (h igh) during deselect; data bus inputs are switching. hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 90 rev. 1.03, 2005-12 06302005-ses0-fm0m 3. definitions for idd: low is defined as vin = 0.4 vddq; high is defined as v in = v ddq ; table is defined as inputs are stable at a high level. switching is defined as inputs are changing between high and low every clock cycle for address and control signals, and inputs changing 50% of each data transfer for dq signals. data sheet 91 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.12 ac timings (h yb18h256321af?12/14/16) table 38 timing parameters (hyb18h256321af?12/14/16) parameter cas latency symbol limit values unit note ?12 ?14 ?16 min max min max min max clock and clock enable system frequency cl= 11 f ck11 400 800 400 700 mhz 1) cl =10 f ck10 400 700 400 650 400 600 mhz 1) cl = 9 f ck9 400 650 400 600 400 550 mhz 1) cl = 8 f ck8 400 550 400 500 400 500 mhz 1) cl = 7 f ck7 400 500 400 450 400 450 mhz 1) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.45 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.45 t ck minimum clock half period t hp 0.45 ? 0.45 ? 0.45 0.45 t ck 2) command and address setup and hold timing address/command input setup time t is 0.3 ? 0.35 ? 0.4 ? ns address/command input hold time t ih 0.3 ? 0.35 ? 0.4 ? ns address/command input pulse width t ipw 0.7 ? 0.7 ? 0.7 ? t ck mode register set timing mode register set cycle time t mrd 6?6?6? t ck 3)4) mode register set to read timing t mrdr 12 ? 12 ? 12 ? t ck 3)3) row timing row cycle time t rc 34 ? 30 ? 28 ? t ck row active time t ras 21 ? 18 ? 17 ? t ck 5) act(a) to act(b) command period t rrd 8?7?6? t ck row precharge time t rp 13 ? 12 ? 11 ? t ck row to column delay time for reads t rcdrd 12 ? 11 ? 10 ? t ck row to column delay time for writes t rcdwr t rcdwr(min) = t rcdrd(min) - (wl + 1) t ck t ck column timing cas(a) to cas(b) command period t ccd 2?2?2? t ck 6) write to read command delay t wtr 6?5?5? t ck 7) read to write command delay t rtw t rtw (min)= (cl + bl/2 +2 -wl) t ck 8) write cycle timing parameters for data and data strobe write command to first wdqs latching transition t dqss wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 t ck data-in and data mask to wdqs setup time t ds 0.16 ? 0.18 ? 0.20 ? ns data-in and data mask to wdqs hold time t dh 0.16 ? 0.18 ? 0.20 ? ns hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 92 rev. 1.03, 2005-12 06302005-ses0-fm0m data-in and dm input pulse width (each input) t dipw 0.40 ? 0.40 ? 0.40 ? t ck dqs input low pulse width t dqsl 0.40 ? 0.40 ? 0.40 ? t ck dqs input high pulse width t dqsh 0.40 ? 0.40 ? 0.40 ? t ck dqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery time t wr 9?8?7? t ck 7) read cycle timing parameters for data and data strobe data access time from clock t ac -0.22 0.22 ?0.25 0.25 ?0.28 0.28 ns read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t acmin t acmax t acmin t acmax t acmin t acmax ns data-out low impedance time from clk t lz t acmin t acmax t acmin t acmax t acmin t acmax ns dqs edge to clock edge skew t dqsck -0.22 0.22 ?0.25 0.25 ?0.28 0.28 ns dqs edge to output data edge skew t dqsq ? 0.140 ? 0.160 ? 0.180 ns 9) data hold skew factor t qhs ? 0.140 ? 0.160 ? 0.180 ns data output hold time from dqs t qh t hp ? t qhs t hp ? t qhs t hp ? t qhs ns refresh/power down timing refresh period (4096 cycles) t ref ?32?32?32 ms average periodic auto refresh interval t refi 7.8 7.8 7.8 s delay from aref to next act/ aref t rfc 52.0 ? 52.0 ? 52.8 ? ns self refresh exit time t xsc 1000 ? 1000 ? 1000 ? t ck power down exit time t xpn 7?6?5? t ck other timing parameters res to cke setup timing t ats 10 ? 10 ? 10 ? ns res to cke hold timing t ath 10 ? 10 ? 10 ? ns termination update keep out timing t ko 10 ? 10 ? 10 ? ns rev. id emrs to dq on timing t ridon ?20?20?20 ns rev. id emrs to dq off timing t ridoff ?20?20?20 ns 1) dllon mode (-12/-14/-16 min. 400mhz) 2) t hp is the lesser of t cl minimum and t ch minimum actually applied to the device clk, clk inputs 3) this value of tmrd applies only to the case where the ?dll reset? bit is not activated. 4) tmrd is defined from mrs to any other command then read. 5) t ras,max is 8* t refi 6) t ccd is either for gapless consecutive read s or gapless consecutive writes. bl =4 7) wtr and t wr start at the first rising edge of clk after the last valid (falling) wdqs edge of the slowest wdqs signal. table 38 timing parameters (hyb18h256321af?12/14/16) parameter cas latency symbol limit values unit note ?12 ?14 ?16 min max min max min max data sheet 93 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 5.13 ac timings (h yb18h256321afl14/16/20) 8) please round up t rtw to the next integer of t ck . 9) this parameter is defined per byte. table 39 timing parameters (hyb18h256321afl14/16/20) parameter cas latency symbol limit values unit notes ?14 ?16 ?20 min max min max min max clock and clock enable system frequency cl = 11 f ck11 350 700 350 600 mhz 1) cl = 10 f ck10 350 650 350 550 350 500 mhz 1) cl = 9 f ck9 350 600 350 500 350 450 mhz 1) cl = 8 f ck8 350 500 350 450 350 400 mhz 1) cl = 7 f ck7 350 450 350 400 350 350 mhz 1) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck minimum clock half period t hp 0.45 ? 0.45 ? 0.45 ? t ck 2) command and address setup and hold timing address/command input setup time t is 0.35 ? 0.4 ? 0.5 ? ns address/command input hold time t ih 0.35 ? 0.4 ? 0.5 ? ns address/command input pulse width t ipw 0.7 ? 0.7 ? 0.7 ? t ck mode register set timing mode register set cycle time t mrd 6?6?6? t ck mode register set to read timing t mrdr 12 ? 12 ? 12 ? t ck row timing row cycle time t rc 30 ? 28 ? 23 ? t ck row active time t ras 18 ? 17 ? 14 ? t ck 3) act(a) to act(b) command period t rrd 7?6?5? t ck row precharge time t rp 12 ? 11 ? 9 ? t ck 5)5) row to column delay time for reads t rcdrd 11 ? 10 ? 8 ? t ck row to column delay time for writes t rcdwr t rcdwr(min) = t rcdrd(min) - (wl + 1) t ck t ck column timing cas(a) to cas(b) command period t ccd 2?2?2? t ck 4) write to read command delay t wtr 5?5?4? t ck 5) read to write command delay t rtw t rtw (min)= (cl + bl/2 +2 -wl) t ck 6) write cycle timing parameters for data and data strobe write command to first wdqs latching transition t dqss wl? 0.25 wl+0. 25 wl? 0.25 wl+0 .25 wl - 0.25 wl +0.25 t ck hyb18h256321af[l] 256-mbit gddr3 electrical characteristics data sheet 94 rev. 1.03, 2005-12 06302005-ses0-fm0m data-in and data mask to wdqs setup time t ds 0.18 ? 0.20 ? 0.24 ? ns data-in and data mask to wdqs hold time t dh 0.18 ? 0.20 ? 0.24 ? ns data-in and dm input pulse width (each input) t dipw 0.40 ? 0.40 ? 0.40 ? t ck dqs input low pulse width t dqsl 0.40 ? 0.40 ? 0.40 ? t ck dqs input high pulse width t dqsh 0.40 ? 0.40 ? 0.40 ? t ck dqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery time t wr 8?7?6? t ck 7) read cycle timing parameters for data and data strobe data access time from clock t ac ?0.25 0.25 ?0.28 0.28 ?0.35 0.35 ns read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t acmin t acmax t acmin t acmax t acmin t acmax ns data-out low impedance time from clk t lz t acmin t acmax t acmin t acmax t acmin t acmax ns dqs edge to clock edge skew t dqsck ?0.25 0.25 ?0.28 0.28 ?0.35 0.35 ns dqs edge to output data edge skew t dqsq ? 0.160 ? 0.18 ? 0.225 ns 7) data hold skew factor t qhs ? 0.160 ? 0.18 ? 0.225 ns data output hold time from dqs t qh t hp ? t qhs t hp ? t qhs t hp ? t qhs ns refresh/power down timing refresh period (4096 cycles) t ref ?32?32?32ms average periodic auto refresh interval t refi 7.8 7.8 7.8 s delay from aref to next act/ aref t rfc 52.0 ? 52.8 ? 54 ? ns self refresh exit time t xsc 1000 ? 1000 ? 1000 ? t ck power down exit time t xpn 6?5?4? t ck other timing parameters res to cke setup timing t ats 10 ? 10 ? 10 ? ns res to cke hold timing t ath 10 ? 10 ? 10 ? ns termination update keep out timing t ko 10 ? 10 ? 10 ? ns rev. id emrs to dq on timing t ridon ?20?20?20ns rev. id emrs to dq off timing t ridoff ?20?20?20ns 1) dllon mode (-14/-16/-20 min. 350mhz) table 39 timing parameters (hyb18h256321afl14/16/20) parameter cas latency symbol limit values unit notes ?14 ?16 ?20 min max min max min max data sheet 95 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 electrical characteristics 2) t hp is the lesser of t cl minimum and t ch minimum actually applied to the device clk, clk inputs 3) t ras,max is 8* t refi 4) t ccd is either for gapless consecutive read s or gapless consecutive writes. bl =4 5) wtr and t wr start at the first rising edge of clk after the last valid (falling) wdqs edge of the slowest wdqs signal. 6) please round up t rtw to the next integer of t ck . 7) this parameter is defined per byte. hyb18h256321af[l] 256-mbit gddr3 package data sheet 96 rev. 1.03, 2005-12 06302005-ses0-fm0m 6 package 6.1 package outline figure 69 pg-tfbga 136 package (11mm x 14mm) note: . the package is conformi ng with jedec mo-207i, var dr-z. data sheet 97 rev. 1.03, 2005-12 06302005-ses0-fm0m hyb18h256321af[l] 256-mbit gddr3 package 6.2 package thermal characteristics 1. theta_ja: junction to ambient ther mal resistance. the values have been obtained by simulation using the conditions stated in th e jedec jesd-51 standard. 2. theta_jb: junction to board thermal resistance . the value has been obtained by simulation. 3. theta_jc: junction to case thermal resistan ce. the value has been obtained by simulation. table 40 pg-tfbga 136 package thermal resistances theta_ja theta_jb theta_jc jedec board 1s0p 2s0p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s - - k/w 4032272219175 2 published by infineon technologies ag www.infineon.com |
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